Hello I'm working on to a project to download this core in Altera FPGA (Quartus II v.11). I'm trying some difficults in add an altera ram to supply dpram.v because I don't know how to deal with the option "bit addressable" and the signals bit_in and wr_bit.

The options that I selected are the next:

RAM: 2-port:
-One read port and one wirte port
-How many 8-bit words of memory? 256
-How wide should the 'data_a' input bus be? 8
-Dual dock: use separate 'read' and 'write' clocks
-Read output port(s)

Do you have any suggestion about how I need to set up altera RAM ? How to handle with the bit_in and wr_bit signals ??

Thanks for your replay.

Hi,

go to www.slscorp.com site and there you will get USB RAM based SOPC reference design. for access design you must create account and login.

Regards,

RC

Hello, again!

I added a dpram memory . I'm trying to simulate with the project files (xrom and rom project files) and I don't know why.

The modelsim message is:

# *
# * External rom interface: Pipelined interface
# *
#
# Program running from internal rom !
#
# progran execution from external rom
# time 2666 faulire: invalid write to ACC (oc8051_acc)
# ** Note: $finish : /home/smorlans/Escritorio/pruebas/modelsim/oc8051_acc.v(140)
# Time: 2688 ns Iteration: 0 Instance: /oc8051_tb/oc8051_top_1/oc8051_sfr1/oc8051_acc1

and the project tree is:

oc8051_tb
+--oc8051_xrom1
+--oc8051_xram1
+--oc8051_uart_test1
+--oc8051_top1
+--oc8051_sfr1
+--oc8051_rom1
+--oc8051_ram_top1
+--oc8051_memory_interface
+--oc8051_indi_addr1
+--oc8051_decoder1
+--oc8051_gy_select1
+--oc8051_comp1
+--oc8051_alu_src_sel1
+--oc8051_alu1

In the oc8051_tb reads the next configuration file:

$readmemb("./in/oc8051_eai.in", ea)

and the oc8051_rom:

$readmemh("./in/oc8051_rom.in", buff);


Thanks for your replay.