Hi all,

I am using VGA/LCD IP core from Richard Herveille on Lattice FPGA using VHDL. My system consists of 32-bit Soft-core Processor Camera, GPIO and LCD modules.

After I ported the VGA/LCD core to my system, I found out that 3 registers, which are VBARa, VBARb and CBAR do not work, means, there is no data transfer to those registers. I checked with the oscilloscope using test pins. As well as, the master port is not read, means, data (pixel) from the processor is not fetched to the core. However, control register (VGA_CTRL), horizontal (VGA_HTIM), vertical (VGA_VTIM) timing registers work well.

I activate the LCD by following commands:

WRITE_ADDR(DISPLAY_BASE_ADDRESS+OC_VGA_CTRL) &= 0xFFFFFFFE; // pause the LCD
WRITE_ADDR(DISPLAY_BASE_ADDRESS+OC_VGA_VBARA) = selectedLCDbuffer; // VBARA
WRITE_ADDR(DISPLAY_BASE_ADDRESS+OC_VGA_VBARB) = selectedLCDbuffer; // VBARB
WRITE_ADDR(DISPLAY_BASE_ADDRESS+OC_VGA_HVLEN) = 0x016200FB; // HVLEN
WRITE_ADDR(DISPLAY_BASE_ADDRESS+OC_VGA_VTIM) = 0x010500EF; // VTIM
WRITE_ADDR(DISPLAY_BASE_ADDRESS+OC_VGA_HTIM) = 0x120C013F; // HTIM
WRITE_ADDR(DISPLAY_BASE_ADDRESS+OC_VGA_CTRL) |= 0x00000001; // activate the LCD

and the IP core remain unchanged.

Anybody has any clue, why those 3 registers do not work and how can I fix it? Do I really need 2 resets, nReset and RST_I on FPGA?

Many thanks in advance and have a nice day :D