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Wishbone interface between two devices

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Wishbone interface between two devices by Unknown on Dec 1, 2004			Not available!
Hello I have seen that the majority of the available IP cores are using the wishbone interface. But I must implement an ethernet MAC core (for example) in a FPGA with an external microprocessor. In fact, I only have a standard memory interface between my FPGA and the Microprocessor. Is the Wishbone interface usable and How to interface the two components? Thanks Bumkele Hello I have seen that the majority of the available IP cores are using the wishbone interface. But I must implement an ethernet MAC core (for example) in a FPGA with an external microprocessor. In fact, I only have a standard memory interface between my FPGA and the Microprocessor. Is the Wishbone interface usable and How to interface the two components? Thanks Bumkele

Wishbone interface between two devices by Unknown on Dec 7, 2004			Not available!
Let's continue on your example, the ethernet MAC. The ethernet MAC has a wishbone bus, it has been used and extensively tested with this bus. So you do not want to touch this, unless you have a very profound reason. In your case the simplest solution is to create a new IP core with two ports; the microprocessor bus, and a wishbone bus. This IP core bridges the wishbone bus to the microprocessor bus; hence the naming "bridges" for this type of IP. So the basic operation is as follows, the microprocessor asserts signals on its bus, the bridge translates these into wishbone signals, and the ethernet MAC responds to these. Any signals from the ethernet MAC enter the bridge, are translated to signals on the microprocessor bus, and the mcu responds to these. There are a couple of examples for different types of microprocessor to wishbone bridges on OpenCores (motorola coldfire, TI dsp, etc). Hope this helps, Richard [q] -----Original Message----- From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at opencores.org</A> [mailto:<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at opencores.org</A>] On Behalf Of <A HREF="http://www.opencores.org/mailman/listinfo/cores">bumkele at yahoo.fr</A> Sent: Wednesday, December 01, 2004 3:24 PM To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Subject: [oc] Wishbone interface between two devices Hello I have seen that the majority of the available IP cores are using the wishbone interface. But I must implement an ethernet MAC core (for example) in a FPGA with an external microprocessor. In fact, I only have a standard memory interface between my FPGA and the Microprocessor. Is the Wishbone interface usable and How to interface the two components? Thanks Bumkele _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] Let's continue on your example, the ethernet MAC. The ethernet MAC has a wishbone bus, it has been used and extensively tested with this bus. So you do not want to touch this, unless you have a very profound reason. In your case the simplest solution is to create a new IP core with two ports; the microprocessor bus, and a wishbone bus. This IP core bridges the wishbone bus to the microprocessor bus; hence the naming "bridges" for this type of IP. So the basic operation is as follows, the microprocessor asserts signals on its bus, the bridge translates these into wishbone signals, and the ethernet MAC responds to these. Any signals from the ethernet MAC enter the bridge, are translated to signals on the microprocessor bus, and the mcu responds to these. There are a couple of examples for different types of microprocessor to wishbone bridges on OpenCores (motorola coldfire, TI dsp, etc). Hope this helps, Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of bumkele at yahoo.fr Sent: Wednesday, December 01, 2004 3:24 PM To: cores at opencores.org Subject: [oc] Wishbone interface between two devices Hello I have seen that the majority of the available IP cores are using the wishbone interface. But I must implement an ethernet MAC core (for example) in a FPGA with an external microprocessor. In fact, I only have a standard memory interface between my FPGA and the Microprocessor. Is the Wishbone interface usable and How to interface the two components? Thanks Bumkele _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Wishbone interface between two devices by Unknown on Dec 7, 2004			Not available!
You'll need to add something to bridge WB interface to your memory interface or you can change the eth_wishbone.v module. WB is pretty simple bus, find more details about it on the opencores website. Regards, Igor On Wed, 1 Dec 2004 15:24:17 +0100, <A HREF="http://www.opencores.org/mailman/listinfo/cores">bumkele at yahoo.fr</A> <<A HREF="http://www.opencores.org/mailman/listinfo/cores">bumkele at yahoo.fr</A>> wrote: [q] Hello I have seen that the majority of the available IP cores are using the wishbone interface. But I must implement an ethernet MAC core (for example) in a FPGA with an external microprocessor. In fact, I only have a standard memory interface between my FPGA and the Microprocessor. Is the Wishbone interface usable and How to interface the two components? Thanks Bumkele _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] You'll need to add something to bridge WB interface to your memory interface or you can change the eth_wishbone.v module. WB is pretty simple bus, find more details about it on the opencores website. Regards, Igor On Wed, 1 Dec 2004 15:24:17 +0100, bumkele at yahoo.fr bumkele at yahoo.fr> wrote: Hello I have seen that the majority of the available IP cores are using the wishbone interface. But I must implement an ethernet MAC core (for example) in a FPGA with an external microprocessor. In fact, I only have a standard memory interface between my FPGA and the Microprocessor. Is the Wishbone interface usable and How to interface the two components? Thanks Bumkele _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

Wishbone interface between two devices by Unknown on Dec 7, 2004			Not available!
Hi Bumkele! You can see the Wishbone specification and you'll find that Wishbone is conceived as a System On Chip Interconnect Architecture. So you'll find it SO useful as is. If you like to interconect an Wishbone Compatible IP with an external Microprocessor, and your Microprocessor isn't Wishbone Compatible you'll have to put your IP Core and a Wishbone-to-MicroprocessorArchitecture Bridge boht togheter in a FPGA :) Best regards, <A HREF="http://www.opencores.org/mailman/listinfo/cores">bumkele at yahoo.fr</A> escribiÃ³: [q] Hello I have seen that the majority of the available IP cores are using the wishbone interface. But I must implement an ethernet MAC core (for example) in a FPGA with an external microprocessor. In fact, I only have a standard memory interface between my FPGA and the Microprocessor. Is the Wishbone interface usable and How to interface the two components? Thanks Bumkele [/q] -- TÃ©cnico AndrÃ©s Trapanotto INSTITUTO NACIONAL DE TECNOLOGÃA INDUSTRIAL Centro de InvestigaciÃ³n Telecomunicaciones, ElectrÃ³nica e InformÃ¡tica TelÃ©fono (54 11) 4724 6300 Interno 6362 <A HREF="http://www.opencores.org/mailman/listinfo/cores">andres_t at inti.gov.ar</A> ___________________________________________ 0800 444 4004 \| www.inti.gov.ar Hi Bumkele! You can see the Wishbone specification and you'll find that Wishbone is conceived as a System On Chip Interconnect Architecture. So you'll find it SO useful as is. If you like to interconect an Wishbone Compatible IP with an external Microprocessor, and your Microprocessor isn't Wishbone Compatible you'll have to put your IP Core and a Wishbone-to-MicroprocessorArchitecture Bridge boht togheter in a FPGA :) Best regards, bumkele at yahoo.fr escribiÃ³: Hello I have seen that the majority of the available IP cores are using the wishbone interface. But I must implement an ethernet MAC core (for example) in a FPGA with an external microprocessor. In fact, I only have a standard memory interface between my FPGA and the Microprocessor. Is the Wishbone interface usable and How to interface the two components? Thanks Bumkele -- TÃ©cnico AndrÃ©s Trapanotto INSTITUTO NACIONAL DE TECNOLOGÃA INDUSTRIAL Centro de InvestigaciÃ³n Telecomunicaciones, ElectrÃ³nica e InformÃ¡tica TelÃ©fono (54 11) 4724 6300 Interno 6362 andres_t at inti.gov.ar ___________________________________________ 0800 444 4004 \| www.inti.gov.ar

Wishbone interface between two devices by Unknown on Dec 13, 2004			Not available!
Thanks for your answer. But I am sorry, but I didn't find any wishbone bridge on the opencores website (I have search with the "coldfire" search word for example). In fact, I would like to evaluate the difficulty of doing a wishbone bridge (time elapsed). Has anyone doing this kind of cores? Thanks Bumkele ----- Original Message ----- From: Richard Herveille<<A HREF="http://www.opencores.org/mailman/listinfo/cores">richard at h...</A>> To: Date: Tue Dec 7 08:31:57 CET 2004 Subject: [oc] Wishbone interface between two devices [q] Let's continue on your example, the ethernet MAC. The ethernet MAC has a wishbone bus, it has been used and extensively tested with this bus. So you do not want to touch this, unless you have a very profound reason. In your case the simplest solution is to create a new IP core with two ports; the microprocessor bus, and a wishbone bus. This IP core bridges the wishbone bus to the microprocessor bus; hence the naming "bridges" for this type of IP. So the basic operation is as follows, the microprocessor asserts signals on its bus, the bridge translates these into wishbone signals, and the ethernet MAC responds to these. Any signals from the ethernet MAC enter the bridge, are translated to signals on the microprocessor bus, and the mcu responds to these. There are a couple of examples for different types of microprocessor to wishbone bridges on OpenCores (motorola coldfire, TI dsp, etc). Hope this helps, Richard [q]> -----Original Message----- > From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at o...</A> > [mailto:<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at o...</A>] On Behalf Of [/q] <A HREF="http://www.opencores.org/mailman/listinfo/cores">bumkele at y...</A> [q]> Sent: Wednesday, December 01, 2004 3:24 PM > To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> > Subject: [oc] Wishbone interface between two devices > > Hello > > I have seen that the majority of the available IP cores are > using the wishbone interface. > But I must implement an ethernet MAC core (for example) in a > FPGA with an external microprocessor. In fact, I only have a > standard memory interface between my FPGA and the [/q] Microprocessor. [q]> > Is the Wishbone interface usable and How to interface the two > components? > > Thanks > > Bumkele > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> > [/q] [/q] Thanks for your answer. But I am sorry, but I didn't find any wishbone bridge on the opencores website (I have search with the "coldfire" search word for example). In fact, I would like to evaluate the difficulty of doing a wishbone bridge (time elapsed). Has anyone doing this kind of cores? Thanks Bumkele ----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Tue Dec 7 08:31:57 CET 2004 Subject: [oc] Wishbone interface between two devices Let's continue on your example, the ethernet MAC. The ethernet MAC has a wishbone bus, it has been used and extensively tested with this bus. So you do not want to touch this, unless you have a very profound reason. In your case the simplest solution is to create a new IP core with two ports; the microprocessor bus, and a wishbone bus. This IP core bridges the wishbone bus to the microprocessor bus; hence the naming "bridges" for this type of IP. So the basic operation is as follows, the microprocessor asserts signals on its bus, the bridge translates these into wishbone signals, and the ethernet MAC responds to these. Any signals from the ethernet MAC enter the bridge, are translated to signals on the microprocessor bus, and the mcu responds to these. There are a couple of examples for different types of microprocessor to wishbone bridges on OpenCores (motorola coldfire, TI dsp, etc). Hope this helps, Richard > -----Original Message----- > From: cores-bounces at o... > [mailto:cores-bounces at o...] On Behalf Of bumkele at y... > Sent: Wednesday, December 01, 2004 3:24 PM > To: cores at o... > Subject: [oc] Wishbone interface between two devices > > Hello > > I have seen that the majority of the available IP cores are > using the wishbone interface. > But I must implement an ethernet MAC core (for example) in a > FPGA with an external microprocessor. In fact, I only have a > standard memory interface between my FPGA and the Microprocessor. > > Is the Wishbone interface usable and How to interface the two > components? > > Thanks > > Bumkele > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores >

Wishbone interface between two devices by Unknown on Dec 15, 2004			Not available!
Let's see, this took 1 minute and 3 mouse clicks to find; TI DSP to OpenCores PCI bridge: <A HREF="http://www.opencores.org/projects.cgi/web/wb2hpi/overview">http://www.opencores.org/projects.cgi/web/wb2hpi/overview</A> Dragonball-Wishbone bridge: <A HREF="http://www.opencores.org/projects.cgi/web/wbif_68k/overview">http://www.opencores.org/projects.cgi/web/wbif_68k/overview</A> Cheers, Richard [q] -----Original Message----- From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at opencores.org</A> [mailto:<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at opencores.org</A>] On Behalf Of <A HREF="http://www.opencores.org/mailman/listinfo/cores">bumkele at yahoo.fr</A> Sent: Monday, December 13, 2004 8:47 AM To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at opencores.org</A> Subject: Re: [oc] Wishbone interface between two devices Thanks for your answer. But I am sorry, but I didn't find any wishbone bridge on the opencores website (I have search with the "coldfire" search word for example). In fact, I would like to evaluate the difficulty of doing a wishbone bridge (time elapsed). Has anyone doing this kind of cores? Thanks Bumkele ----- Original Message ----- From: Richard Herveille<<A HREF="http://www.opencores.org/mailman/listinfo/cores">richard at h...</A>> To: Date: Tue Dec 7 08:31:57 CET 2004 Subject: [oc] Wishbone interface between two devices [q]> Let's continue on your example, the ethernet MAC. > The ethernet MAC has a wishbone bus, it has been used and [/q] extensively [q]> tested with this bus. > So you do not want to touch this, unless you have a very profound > reason. > In your case the simplest solution is to create a new IP [/q] core with two [q]> ports; the microprocessor bus, and a wishbone bus. This IP core > bridges the wishbone bus to the microprocessor bus; hence [/q] the naming [q]> "bridges" for this type of IP. > So the basic operation is as follows, the microprocessor asserts > signals on its bus, the bridge translates these into [/q] wishbone signals, [q]> and the ethernet MAC responds to these. Any signals from [/q] the ethernet [q]> MAC enter the bridge, are translated to signals on the [/q] microprocessor [q]> bus, and the mcu responds to these. > There are a couple of examples for different types of [/q] microprocessor [q]> to wishbone bridges on OpenCores (motorola coldfire, TI dsp, etc). > Hope this helps, > Richard [q] > -----Original Message----- > From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at o...</A> > [mailto:<A HREF="http://www.opencores.org/mailman/listinfo/cores">cores-bounces at o...</A>] On Behalf Of[/q] > <A HREF="http://www.opencores.org/mailman/listinfo/cores">bumkele at y...</A> [q] > Sent: Wednesday, December 01, 2004 3:24 PM > To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> > Subject: [oc] Wishbone interface between two devices > > Hello > > I have seen that the majority of the available IP cores are using > the wishbone interface. > But I must implement an ethernet MAC core (for example) in a FPGA > with an external microprocessor. In fact, I only have a standard > memory interface between my FPGA and the[/q] > Microprocessor. [q] > > Is the Wishbone interface usable and How to interface the two > components? > > Thanks > > Bumkele > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> > [/q] > > [/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] Let's see, this took 1 minute and 3 mouse clicks to find; TI DSP to OpenCores PCI bridge: http://www.opencores.org/projects.cgi/web/wb2hpi/overview Dragonball-Wishbone bridge: http://www.opencores.org/projects.cgi/web/wbif_68k/overview Cheers, Richard -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of bumkele at yahoo.fr Sent: Monday, December 13, 2004 8:47 AM To: cores at opencores.org Subject: Re: [oc] Wishbone interface between two devices Thanks for your answer. But I am sorry, but I didn't find any wishbone bridge on the opencores website (I have search with the "coldfire" search word for example). In fact, I would like to evaluate the difficulty of doing a wishbone bridge (time elapsed). Has anyone doing this kind of cores? Thanks Bumkele ----- Original Message ----- From: Richard Herveillerichard at h...> To: Date: Tue Dec 7 08:31:57 CET 2004 Subject: [oc] Wishbone interface between two devices > Let's continue on your example, the ethernet MAC. > The ethernet MAC has a wishbone bus, it has been used and extensively > tested with this bus. > So you do not want to touch this, unless you have a very profound > reason. > In your case the simplest solution is to create a new IP core with two > ports; the microprocessor bus, and a wishbone bus. This IP core > bridges the wishbone bus to the microprocessor bus; hence the naming > "bridges" for this type of IP. > So the basic operation is as follows, the microprocessor asserts > signals on its bus, the bridge translates these into wishbone signals, > and the ethernet MAC responds to these. Any signals from the ethernet > MAC enter the bridge, are translated to signals on the microprocessor > bus, and the mcu responds to these. > There are a couple of examples for different types of microprocessor > to wishbone bridges on OpenCores (motorola coldfire, TI dsp, etc). > Hope this helps, > Richard > -----Original Message----- > From: cores-bounces at o... > [mailto:cores-bounces at o...] On Behalf Of > bumkele at y... > Sent: Wednesday, December 01, 2004 3:24 PM > To: cores at o... > Subject: [oc] Wishbone interface between two devices > > Hello > > I have seen that the majority of the available IP cores are using > the wishbone interface. > But I must implement an ethernet MAC core (for example) in a FPGA > with an external microprocessor. In fact, I only have a standard > memory interface between my FPGA and the > Microprocessor. > > Is the Wishbone interface usable and How to interface the two > components? > > Thanks > > Bumkele > _______________________________________________ > http://www.opencores.org/mailman/listinfo/cores > > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

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