I want to design a z80 on my FPGA (Diligent Nexsys 2).
I'm getting a bit stuck.
Does anyone have any ideas on how I should start?

What I've done so far:
I've obtained a couple of books on the Z80 from the 1980's.
They are more from a programmers stand point though.

This depends strongly on what you've done before with respect to implementing CPU architectures. You will need a precise definition of the instruction set; the following data book is a start:

http://www.bitsavers.org/pdf/zilog/z80

I assume that you've read Hennessy & Patterson's great book on "Computer Organization and Design"? Pick an implementation strategy (multi-cycle is probably easiest) and prepare for weeks of writing HDL descriptions. It will help to have a software emulation of the Z80 alongside, so that you can verify the behavior of your implementation with (very many) small test programs.

Hellwig

Hi,
A useful reference would be the new book published by Circuit Cellar: "Microprocessor Design Using Verilog HDL"

http://circuitcellar.com/editorsblog/microprocessor-design-using-verilog-hdl/

The running example in the book is a complete implementation of the Z80.

(I have no connection with the author or publisher, I have just read the book and I liked it)
Tony Williamitis

Thank you for sharing this. I used to the "build you own Z80" books from them to get into digital design
in the early 80's so this is Kharma :-) I do VHDL and verilog now so I have to get it to review.

If your design is not around the Z80 core but around peripherals see the Z80 SOC project :
http://opencores.org/project,z80soc

Thanks for the replies. :)
Now I have somewhere to get started.
Will definitely hit those resources up.

To run example you should do some work to copy/edit/etc (author says, that it is a week time of work), because control.v attached to a book is truncated. Also this file can be purchased from author for $995. Moreover, Y80 has no support for undocumented instructions (like halfs of index registers).

Next z80 implementations available on OpenCores:
T80 - original timings, VHDL (we cannot run it)
TV80 - same as T80, but Verilog
NextZ80 - boosted Z80 (most one byte ops executes at one clk)
wb_z80 - wishbone compiant Z80. I think, this CPU is not properly tested.

Thats strange. Usually the example code published in a book is also made available for free to save the readers from having to retype it in.


John Eaton

The $995 I think is if Monty has to create the entire project for you instead of
you collecting the files yourself into your flow. Just my guess.

Before I post message here I did ask authon about this problem.
if him publish full code of cpu, then most potential book-buyers simply download files. this is main reason.

You can try to simulate any op on Y80. For example, simulate E5 (PUSH HL). This op does 2 write operations... in theory. Y80 NEVER rises wr line.

Check out this one
This one is too good...
http://www.geocities.jp/kwhr0/hard/fz80.v.gz