OpenCores
Home » All forums » Cores » Core for support vector machine in verilog
no use no use 1/1 no use no use
Core for support vector machine in verilog
by hallolo on Feb 22, 2012 		hallolo
Posts: 1
Joined: Jul 22, 2009
Last seen: Feb 22, 2012
Hello everybody

Could somebody advise on where to find a verilog code (IP core) for Support vector machine classifier (SVM)?

Reagrds

Hallolo
no use no use 1/1 no use no use
© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.