Dear all,

I was searching for an SPI core, when I stumbled into the core available on this website at the following link http://opencores.org/project,spi,overview, by author Simons Srot.

Unfortunately though, I cannot understand which are the files which actually make up the core because there are a lot of .v files stored at different sub folders.

So if there are any of you have tried this out, please reply with some hints :)

Thanks for your time.

regards.

.v files which is in trunk/rtl/verilog are core related file.

that .v files are verilog files by using any software that supports verilog files like modelsim,xilinx, you can open those files
.v files for the verilog files and .vhd for vhdl files