hi, i am using an old book, it says that only output ports can be declared as registers.is it true for the new verilog?

The defining property of a reg is that it can be assigned by an always block. If that assignment reacts to a clock edge then the reg will be a register. Since inputs cannot be assigned, they cannot be reg. You can certainly declare another reg inside your module and use an always block to transfer data, thus creating an input register or buffer.

The respondent is correct - but I know whst he is trying to say and think it a bit confusing. So - the simple answer is yes you can put a register on an input or output - but it is a separate declaration from the I/O itself. Does that clear it up.

Assume something like:

module test (clk,reset,input_pin, output_pin,.... );

reg rcv_input_pin;
reg output_pin;

always @(posedge clk or posedge reset)
if(reset)
begin
output_pin rcv_input_pin end
else
begin
output_pin rcv_input_pin end

A register can directly drive an output - an input_pin needs to be received by a reg variable separately declared from the input pin. Hope this example helps.

Actually we dont need an input to be reg. If you want to use reg then transfer input to a reg. reg is used to latch data as always block executes only for an instant.