Hi all:

The "OpenCores HDL modeling guidelines" document states the following:

--------82. Recommendation: Use non-blocking assignment (synchronous process, and blocking assignment (=) in asynchronous
process.
Synopsys expects this format. Makes the simulation respond more
deterministically.
--------8
I'm getting one Verilator warning per "#1" in the source code, and, after talking to a number of more experienced people, it looks like it is a remmant of the past that should be taken away. A plain "
Here is some more background information on this matter: The "#1" bit will make the Icarus simulation differ from the synthesis, as both the synthesiser and Verilator ignore it. How much time #1 actually means depends on the current timescale, which is probably not what originally intended.

Regards,
R. Diez

I'm sorry that the original post was garbled, something is not quite right with the forum web interface. I'm trying again:

Hi all:

The "OpenCores HDL modeling guidelines" document states the following:

--------------------------------
2. Recommendation: Use non-blocking assignment (<=#1) in
synchronous process, and blocking assignment (=) in asynchronous
process.
Synopsys expects this format. Makes the simulation respond more
deterministically.
--------------------------------

I'm getting one Verilator warning per "#1" in the source code, and, after talking to a number of more experienced people, it looks like it is a remmant of the past that should be taken away. A plain "<=" is the right thing to do. In fact, the guideline document should probably recommend against using #1 in that way.

Here is some more background information on this matter: The "#1" bit will make the Icarus simulation differ from the synthesis, as both the synthesiser and Verilator ignore it. How much time #1 actually means depends on the current timescale, which is probably not what originally intended.

Regards,
R. Diez