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Running UVM example in System Verilog
by vikramsinghh on Mar 14, 2012 |
vikramsinghh
Posts: 3 Joined: Dec 20, 2011 Last seen: Jan 10, 2013 |
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Hello Everyone,
I am a new learner of system verilog.A task have assigned me for designing a OVM/UVM based simple example, up & running on Aldec Riviera Pro tool.I have downloaded one(attached) which is showing some problem during simulation. It will be very helpful for me if anyone suggest me any other good working example on the same or sort out the problem occurring in attached example Seeking a reply, Thanks in advance Vikram
Simple_Exmp.zip (4 kb)
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RE: Running UVM example in System Verilog
by jt_eaton on Mar 14, 2012 |
jt_eaton
Posts: 142 Joined: Aug 18, 2008 Last seen: Sep 29, 2018 |
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Hello Everyone,
I am a new learner of system verilog.A task have assigned me for designing a OVM/UVM based simple example, up & running on Aldec Riviera Pro tool.I have downloaded one(attached) which is showing some problem during simulation. It will be very helpful for me if anyone suggest me any other good working example on the same or sort out the problem occurring in attached example Seeking a reply, Thanks in advance Vikram
Simple_Exmp.zip (4 kb)
Did you include a log file or screenshot that shows the problem? John Eaton |
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RE: Running UVM example in System Verilog
by vikramsinghh on Mar 15, 2012 |
vikramsinghh
Posts: 3 Joined: Dec 20, 2011 Last seen: Jan 10, 2013 |
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RE: Running UVM example in System Verilog
by kirloy on Jan 31, 2013 |
kirloy
Posts: 2 Joined: Jan 30, 2013 Last seen: Jan 31, 2013 |
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You are initializing design with "testcase " as top level
asim -lib work -t 0 -dataset {E:/SV_Exmp/ones_counter} -datasetname {sim} testcase while testcase is: interface intf_cnt ; .... endinterface program testcase(intf_cnt intf); ... endprogram Interface port cannot be left unconnected so testcase cannot be a toplevel. I assume that what you really want is to use module named "top" as top level - so just try: asim -lib work -t 0 -dataset {E:/SV_Exmp/ones_counter} -datasetname {sim} top |
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RE: Running UVM example in System Verilog
by kirloy on Jan 31, 2013 |
kirloy
Posts: 2 Joined: Jan 30, 2013 Last seen: Jan 31, 2013 |
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You are initializing design with "testcase " as top level
asim -lib work -t 0 -dataset {E:/SV_Exmp/ones_counter} -datasetname {sim} testcase while testcase is: interface intf_cnt ; .... endinterface program testcase(intf_cnt intf); ... endprogram Interface port cannot be left unconnected so testcase cannot be a toplevel. I assume that what you really want is to use module named "top" as top level - so just try: asim -lib work -t 0 -dataset {E:/SV_Exmp/ones_counter} -datasetname {sim} top |
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RE: Running UVM example in System Verilog
by sunildrak on Feb 26, 2013 |
sunildrak
Posts: 3 Joined: Jan 11, 2013 Last seen: Jun 11, 2017 |
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Hello Sir
I am very new to UVM methodology.I am learning it but unable to find any basic example the example that you posted is of counter and can you plz send the full workimg UVM code it will be a great favour plz plz plz sir . In many sites they gave ALU and other very complex DUT as example yours is very basic for learner ..It is very difficult to learn without basic examples.... Thanking You Regards Sunidrak |
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RE: Running UVM example in System Verilog
by dong.nguyen.synapse on Mar 2, 2018 |
dong.nguyen.synapse
Posts: 1 Joined: Feb 1, 2018 Last seen: Mar 2, 2018 |
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Hi Sunidrak,
I think you could use UVM now. Right? If you need more, please give me your email, we can discuss and send data together Thanks, DN |
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RE: Running UVM example in System Verilog
by peermohamed on Mar 13, 2018 |
peermohamed
Posts: 1 Joined: Jul 14, 2011 Last seen: Mar 15, 2021 |
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Hi Sunidrak,
I think you could use UVM now. Right? If you need more, please give me your email, we can discuss and send data together Thanks, DN Sir, I also new to UVM Concepts. Will you help me to learn UVM. my mail ID is peermohamed1989@gmail.com. Thank You |
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