Please help me to get verilog code for a numerically controlled oscillator

waiting for some response............

Nobody can help you with such an incompletely specified task, sorry. Three lines of Verilog code would do the trick: add a constant to a register, every time the next sample is needed. The register represents the phase, the constant determines the frequency. But I doubt that this would solve your problem. At the very least I would expect that you have to do a table lookup to map the phase into the amplitude of, e.g. a sine wave. The details however depend completely on what you are trying to accomplish.

Thanks for the response...
yes,I am using a sine Look up table to convert phase to amplitude but i have a doubt.
As we use the truncated output of phase, what about the error.
and what must be the range of constant(i.e frequency) we use to add at each clock?

waiting for reply

what about error due to truncation?
what is the range of frequency we should use?

The truncation error can be minimized by either using a larger table, or (better) by linear interpolation: multiply the fractional part of the phase with the difference between two consecutive entries in the sine table and add the result to the sine value you looked up in the table under the integral part of the phase. This is most easily done by storing the differences in a second table.

The table stores one complete cycle of the wave (at least in theory - you can get by with a fourth of a cycle because of symmetries). If the sample rate is fs (and thus the sample period is ts = 1/fs), the number of table entrie is n, and the phase increment per sample period is d, then the total time for one cycle of the wave is tw = (ts * n) / d. From that you get the frequency of the generated wave: fw = 1/tw = d / (ts * n) = (d * fs) / n. The absolute values of course depend on your application.

In my project I am using a look up table with 16384 entries..
This is too big . How to reduce it?

Thank you

And my table has integer values. How to convert integer to binary AND vice-versa in verilog

Thank you

https://www.google.com/search?q=DDS+verilog

If this entries is 0-2*pi you can reduce size to quarter.
You need on sin(0) to sin(pi/2) other values you can simple calculated.

Other case is: using Cordic algoritm. This algoritm requiere lookup table sin(0) - sin(pi/8)
http://en.wikipedia.org/wiki/CORDIC

p.s. sorry mi english is terrible

See comments above. Such an oscillator is ridiculously easy to implement.

Have you considered the open core NCO / Periodic Waveform Generator?