dear all,

i've read thru Tom's CF FIR design using the Confluence software.
Anyone knows whether the VHDL coding is suitable for any fixed point
and sign input or it's just limited to the unsign binary?

Besides,can i have further details on the vhdl coding for example the
procedure of the coding?I will be much appreciated if you could provide
further reading material on the design.

Thanks,
Esther

Dear all,
I've read through Tom's CF FIR VHDL generated by the Confluence.

1. Does anyone know whether the coding can support signed fixed point
binary or it's just limited to the unsigned binary inputs?

2. How to decode the result?WHich bit is representing sign bit and how
about overflow?

3. Is there any other reading materials which can help better
comprehending the flow of the coding?

Will be much appreciated for your help.Thanks.

Regards,
Esther

wanderwonderus at yahoo.com wrote: Hi Esther, The core was generated with the following Confluence design. The syntax is a bit out of date, but at only 20 lines of code, it would take all of 5 minutes it bring it inline with the latest version of Confluence. James Gilb has a good table in the documentation comparing pre and post 0.9 syntax. Looking at the MultiplierBank, it appears I used unsigned multipliers. Drop in '*+' if you need signed. Or better yet, make the multiplier operation an input to the FirFilter, so it can be parameterized. For the latest Confluence compiler: http://www.confluent.org/ -Tom component FirFilter +FilterReset +Coefficients +FilterInput -FilterOutput with DelayTaps MultResults is {Reset FilterReset {DelayBank (length Coefficients) FilterInput DelayTaps}} {MultiplierBank Coefficients DelayTaps MultResults} {AdderTree MultResults FilterOutput} end component DelayBank +NumberOfTaps +BankInput -BankOutputs is if NumberOfTaps == 0 BankOutputs