I am trying to figure out an easy way to define vectors in Verilog.
For instance, in the dedsign we have 22-element vectors, each of these
elements are 16-bit wide (22 x 16 = 352 bits). There are 32 such
vectors that I need to store. I am using the following notation for
the memory - MEMA:
Reg [351:0] MEMA [31:0]

Now I need to perform computations using individual elements of the
vector. For instance, I need to add two elements j and k of the vector
(elements are 16-bits wide) from MEMA location p and store the result
in location q.

Is there a simple way of identifying the vector elements and using
them in repetitive computation.

I will appreciate any suggestions on the subject.

Thank you,

Ashim Roy

The answer depends somewhat on whether you want the reuslt to be
synthesizable. The easiest way is to simply access the elements by
bit-slice:

reg [351:0] tmp;

tmp = MEMA[p];
result = tmp[(j+1)*16-1:j*16] + tmp[(k+1)*16-1:k*16];

However, some simulators and most synthesis tools will not accept this
syntax. Shift notation is less intuitive but works better with the
language:

reg [15:0] tmpa, tmpb;
mpa = MEMA[p] >> (j*16);
tmpb = MEMA[p] >> (k*16);
result = tmpa + tmpb;

For synthesis, this might generate acceptable results, but for
hardware it would be better to explicitly declare the two 22:1 muxes
and add the results.

- Guy

Or, best of all, check if your tool chain / design rules allow the use of Verilog 2001 syntax. Verilog 2001 adds support for multidimensional arrays and some other must-have stuff. Many tools seem to support most of it now, eg Xilinx' and Altera's bundled synthesis tools. Google finds many document describing Verilog 2001, e.g.: http://img.cmpnet.com/eedesign/features/Verilog-2001_paper.pdf Best regards Gunnar Dahlgren Quoting Guy Hutchison ghutchis at gmail.com>: ------------------------------------------------- This mail sent through IMP: http://horde.org/imp/