Hi guys,

I'm currently trying to get the AES core at (http://opencores.org/project,avs_aes) up and running on a DE2-70 dev board (Cyclone II). If anyone has experience with this core, any help you can provide is greatly appreciated!

My setup:

I have included the core as a component in QSys and hooked it upto a NIOS2. I can generate the system, and compile/program the device with Quartus. I am now trying to use and verify the core is working by programming the NIOS2 using Altera's Eclipse IDE, deploying included 'AESTester.c' and associated driver files (after updating AES_BASEADDR to match the base address assigned in QSys which is also defined in the BSP system.h).

What is happening:

Running the code results in control being stuck in the first avs_aes_isBusy loop, spamming the debug console with "not ready".
This does not occur in debug mode, however stepping through shows that no result data is being returned after encryption/decryption. I.e., the result buffer is empty/unset {0,0,0,0}.

I'm hoping to use this core as part of a university final year project - don't have too much experience with FPGAs (especially integrating custom cores into a sys).

Thanks

I recall this also happened during my experiments. I think it was related to the adresses assigned in SOPC builder. Unfortunately I don't have an FPGA board at hand to reproduce the issue. I found however in an old project the configuration where I had a 25MHz clock, The Base address was 0x80, End address 0xFF and the IRQ was enabled. I think this configuration worked fine.

To any poor soul who also happens to come across this problem, the resolution in my case ended up being to use the Altera IORD and IOWR macros from io.h.

The standard reads/writes had no affect in my setup. IORD/WR macros translate to instructions which bypass the cache (which may have been the issue).

It may also be possible to utilise the alt_remap_uncached() function to prevent caching of the memory area used by the peripheral.

Hi,

I am trying to use this core and the problem I have is that the busy bit gets reset too quickly. I am running the core at 50MHz which I think is ok given that the test case runs at 100MHz.

Could you kindly post your settings or the software driver for this aes core?

Thanks.
Ramya