Hi, I'm running the RS232 WB controller core as a master (without any
other masters) and its connected to the GPIO WB core. It functions
fine, but I've been noticing that it freezes. I divide a 100 Mhz
clock by 2, 4, or 16, and wether its running at 50Mhz or 6.25Mhz, the
rs232 module stops responding to serial characters usually in under a
minute.

After playing around with it all for a day or two, I've noticed that
when I clock all the components using a global CLK line on the Xilinx
FPGA, that is when it freezes. When I allow it to use a local clock
(with multiple flip flop sources) then its all stable for hours
(ofcourse the skew is really bad ~ 3ns), but it functions fine.

I was wondering if anyone else could tell me how I should next debug
this? I've only taken a single course on FPGAs and VHDL, it was
rather introductory. I think it might be something with hold times?
or setup times? I'm not sure.

I'd be happy to post my VHDL code, if its needed. I'm working on a
Memec Spartan2 200-6 PCI board. Dont know if there is anything else I
can say about my problem.

Thank you for any help,
Mark

UPDATE:
After more experimentation, the core freezes all the time now. I
changed very few things, and re-synthesized the core. And now when
ever I synthesize it with or without using a global clock it freezes
after less then a minute. I still have an old (yesterdays) bit stream
file, that seems to work fine (I let it run for 3 hours without
problems). So I'm really confused. Is there some sort of synthesis
settings I'm not configuring that could be causing this sort of behaviour?

Thank you,
Mark

tc27 at shaw.ca wrote:

I'd guess you have a state machine that depends on an input registered
in a different clock domain to the one the state machine uses.

part of the state machine sees an edge of that signal, and part does
not. Being xilinx, a one-hot state machine has degenerated to the
no-hot state. The fire went out.

solution - always register all signals used to control state machines
with the same clock the state mahine uses to transition.

john

tc27 at shaw.ca wrote:

Loads. You haven't really told us anything. Are you simulating, or
running on real hardware? If you haven't simulated, then go back and do so.

What's on your device? Is it just the RS232 and GPIO? Are these cores
tested and known to work?

BTW, if you haven't got a very good reason not to, then use a global
clock line. Why are you considering using local clocks?

RT

I'm running it on a Memec Spartan2 200 - 6 board that has a MAX232
type part that converts the levels.



The GPIO core looks good, its recent, and very nicely written. The
RS232 Wishbone Controller is a bit old, and not as neatly written.



At first having local clocks actually improved the stability of the
core substantually. But after another couple days, I've determined
that whether its stable or not, completely depends on the synthesis.
Like I said before I'm dividing 100 Mhz by 4 to get a system clock of
25Mhz that is clocking everything inside the FPGA.

At first I did this using one of the Xilinx DLLs, but I noticed
freezing, and thinking that it could be the DLL (or atleast my
implementation of the divider) I switched to a counter to divide the
clock. The first time I syntesized, Xilinx's ISE didnt make the
output a global clock, but everything ran fine. Later I went back and
made it a global clock, but then the RS232 core started freezing.

I did a few tests, then went back to the DLL as a divider (with global
clock output), and it stopped freezing, and worked just fine. Then I
changed a few minor things in my overall design, and it started
freezing again.

I should point out that the RS232 core freezes without asking it to do
any WISHBONE bus transactions. I simply reset the FPGA, hit
and the RS232 core gives me the prompt. Then I keep hitting
(or hold it down) and within a minute it will freeze.

Again, sometimes it will synthesize fine, and will run for hours.
Sometimes ISE synthesizes it in such a way that it freezes within a
minute. Thats why its kinda puzzling me.

Anyways I've moved on and excepted that it freezes, since its only
there for testing purposes. I'm now adding the PCI WISHBONE Bridge as
a guest, and another slave ( the Timer/Counter core ), and using
CONBUS to connect them all.

Thank you all,
Mark

Are you using timing constraints on your design when compiling it through
the backend place and route tools? If not, I suggest learn what they are
and how to use them. Though it may not be (or solve) your problem, it is
important to learn and understand them.

Regards,

Austin