//compute one time need (400+1000+900+400+1000)*50*20(clk)=3 700 000=3.7ms
//tao=0.002s=2sm
// tao should be given sample time
module KF_Filter(
clk,reset,
at_0,
vt_0, // at_0,vt_0 are observes
ke_0, // tire diameter proportion
at_1,
vt_1
);

input clk;
input reset;
input[31:0] at_0; //the sampe value
input[31:0] vt_0;
input[31:0] ke_0;
output[31:0] at_1; //after KF the vector
output[31:0] vt_1;
//output[31:0] ke_1;


reg[31:0] A33[0:8];
reg[31:0] B33[0:8];
reg[31:0] C23[0:5];
reg[31:0] Q3[0:2];//input noise disperturb
reg[31:0] R2[0:1];//output noise disperturb

reg[31:0] XK31_[0:2];
reg[31:0] XK31[0:2];
reg[31:0] Z[0:1]; // measured by outside (observed)
reg[31:0] W[0:2]; //the noise disturb
reg[31:0] P33_[0:8];
reg[31:0] P33[0:8];
reg[31:0] K32[0:5];
////////////////////// initial ///////////////////

reg[31:0] P0[0:8];
//reg[31:0] X0[0:2];//shoule be valued by output measure
reg[0:2] step;
reg step1_start,step2_start,step3_start,step4_start,step5_start;
reg step1_end,step2_end,step3_end,step4_end,step5_end;
reg[0:5] n;
reg[31:0] at;
reg[31:0] vt;
parameter zero=32'h000000,one=32'h3f800000,tao=32'h3B03126F;
//ftao=-0.002
// tao=sample ime > iterative time
initial //A
begin
A33[0]=one;
A33[1]=zero;
A33[2]=zero;
A33[3]=tao;
A33[4]=one;
//A33[5]=zero;//-tao*at_0 when initial at_0=0
A33[6]=zero;
A33[7]=zero;
A33[8]=one;
end
initial //B
begin
B33[0]=tao;
B33[1]=zero;
B33[2]=zero;
B33[3]=32'h3B03126F;//-tao^2/2
B33[4]=tao;
//B33[5]=zero;//(-tao^2/2)*at_0 when initial at_0=0
B33[6]=zero;
B33[7]=zero;
B33[8]=tao;
end

initial //C
begin
C23[0]=one;
C23[1]=zero;
C23[2]=zero;
C23[3]=zero;
C23[4]=one;
C23[5]=zero;////////?????
end
initial //Q
begin
Q3[0]=32'h3B03126F;//1.5
Q3[1]=32'h3C23D70A;//0.01=0+(127-6)+tail=0+0111 1001 +tail
Q3[2]=32'h3C23D70A;//0.0003=0+(127-11)+tail=0+0111 0100 +tail
end
initial //R
begin
R2[0]=32'h3C23D70A;//0.023=0+(127-5)+tail=0+0111 1010+tail
R2[1]=32'h73C23D70A;//0.005=0+(127-7)+tail=0+0111 1000+tail
end
initial //P0
begin
P0[0]=one;
P0[1]=zero;
P0[2]=zero;
P0[3]=zero;
P0[4]=one;
P0[5]=zero;
P0[6]=zero;
P0[7]=zero;
P0[8]=32'h3C23D70A;//0.00001=0+(127-16)+tail=0+0110 1111+tail
end
////////////////// initial end ///////////////

//////////////////Tp renew the modify data

initial begin //P X_
P33[0]=P0[0];
P33[1]=P0[1];
P33[2]=P0[2];
P33[3]=P0[3];
P33[4]=P0[4];
P33[5]=P0[5];
P33[6]=P0[6];
P33[7]=P0[7];
P33[8]=P0[8];
XK31[0]=at_0;///
XK31[1]=vt_0; ////
XK31[2]=ke_0;
end
initial begin //W=0;the disturb is negecect

W[0]=zero;
W[1]=zero;
W[2]=zero;

end

////////////////////// state_MC ///////////////////

//always@(posedge clk or negedge reset)
// if(!reset)step=3'd0;
// else if(step==3'd5) step=3'd0;
// else if(step1_end||step2_end||step3_end||step4_end||step5_end)
// step=step+1'b1;

always@(posedge clk or negedge reset )
if(!reset)begin
step1_start step2_start step3_start step4_start step5_start n=0;
end

else begin
if(n case(step)

3'd0:begin //step1
step1_start step5_start if(step1_end==1)step end
3'd1:begin
step1_start step2_start if(step2_end==1)step end
3'd2:begin
step2_start step3_start if(step3_end==1)step end
3'd3:begin
step3_start step4_start if(step4_end==1)step end
3'd4: begin //step5
step4_start=1'b0;
step5_start=1'b1;
if(step5_end==1)begin step n end
end
default: ;
endcase
end

else n
end

/////////////////////// UPDATA ////////////////////////////////////
//updata B[5]=(-tao^2/2)*at_0(at(K)) A[5]=-tao*vt_0(at(k))
reg ini_start;
wire[31:0] UP_A5;
wire[31:0] UP_B5;
always@( posedge clk)
if(n==6'd0)begin // when initial all the reters are 0
Z[0] Z[1] A33[5] B33[5] end
else if(n==6'd1)begin
ini_start
end
else if(n==6'd2)begin ini_start
UPDATA updata_1(
.start(ini_start),
.clk(clk),
.at0(at_0),
.A5(UP_A5),
.B5(UP_B5)
);


////////////////////////////////////////////////////////////

///////////////Begin to output

assign at_1=at; //after KF the vector
assign vt_1=vt;
//

STEP1 KF_1(
.oclk(clk),
.reset(reset),
.start( step1_start),
.A0(A33[0]),
.A1(A33[1]),
.A2(A33[2]),
.A3(A33[3]),
.A4(A33[4]),
.A5(A33[5]),
.A6(A33[6]),
.A7(A33[7]),
.A8(A33[8]),

.B0(B33[0]),
.B1(B33[1]),
.B2(B33[2]),
.B3(B33[3]),
.B4(B33[4]),
.B5(B33[5]),
.B6(B33[6]),
.B7(B33[7]),
.B8(B33[8]),

.W0(W[0]),
.W1(W[1]),
.W2(W[2]),

.XK_0(XK31[0]),
.XK_1(XK31[1]),
.XK_2(XK31[2]),

.step1_end(step1_end),
.XK0(XK31_[0]), ///the estimate data
.XK1(XK31_[1]),
.XK2(XK31_[2]),

//////////////////////
.at(at),
.vt(vt)
);

STEP2 FK_2( //cmmpute P_
.oclk(clk),
.reset(reset),
.start(step2_start),

.A0(A33[0]),
.A1(A33[1]),
.A2(A33[2]),
.A3(A33[3]),
.A4(A33[4]),
.A5(A33[5]),
.A6(A33[6]),
.A7(A33[7]),
.A8(A33[8]),

.B0(B33[0]),
.B1(B33[1]),
.B2(B33[2]),
.B3(B33[3]),
.B4(B33[4]),
.B5(B33[5]),
.B6(B33[6]),
.B7(B33[7]),
.B8(B33[8]),

.P0(P33[0]),
.P1(P33[1]),
.P2(P33[2]),
.P3(P33[3]),
.P4(P33[4]),
.P5(P33[5]),
.P6(P33[6]),
.P7(P33[7]),
.P8(P33[8]),

.Q0(Q3[0]),
.Q1(Q3[1]),
.Q2(Q3[2]),

.step2_end(step2_end),
.P_0(P33_[0]),
.P_1(P33_[1]),
.P_2(P33_[2]),
.P_3(P33_[3]),
.P_4(P33_[4]),
.P_5(P33_[5]),
.P_6(P33_[6]),
.P_7(P33_[7]),
.P_8(P33_[8])
);

STEP3 KF_3(
.oclk(clk),
.reset(reset),
.start(step3_start),
.C0(C23[0]),
.C1(C23[1]),
.C2(C23[2]),
.C3(C23[3]),
.C4(C23[4]),
.C5(C23[5]),


.P0(P33_[0]),
.P1(P33_[1]),
.P2(P33_[2]),
.P3(P33_[3]),
.P4(P33_[4]),
.P5(P33_[5]),
.P6(P33_[6]),
.P7(P33_[7]),
.P8(P33_[8]),

.R0(R2[0]),
.R1(R2[1]),

.step3_end(step3_end),
.K0(K32[0]),
.K1(K32[1]),
.K2(K32[2]),
.K3(K32[3]),
.K4(K32[4]),
.K5(K32[5])

);

STEP4 KF_4(
.oclk(clk),
.reset(reset),
.start(step4_start),
.X_0(XK31_[0]),
.X_1(XK31_[1]),
.X_2(XK31_[2]),

.Z0(Z[0]),
.Z1(Z[1]),

.K0(K32[0]),
.K1(K32[1]),
.K2(K32[2]),
.K3(K32[3]),
.K4(K32[4]),
.K5(K32[5]),

.step4_end(step4_end),
.X0(XK31[0]),
.X1(XK31[1]),
.X2(XK31[2])

);

STEP5 KF_5(
.oclk(clk),
.reset(reset),
.start(step5_start),

.P_0(P33_[0]),
.P_1(P33_[1]),
.P_2(P33_[2]),
.P_3(P33_[3]),
.P_4(P33_[4]),
.P_5(P33_[5]),
.P_6(P33_[6]),
.P_7(P33_[7]),
.P_8(P33_[8]),

.K0(K32[0]),
.K1(K32[1]),
.K2(K32[2]),
.K3(K32[3]),
.K4(K32[4]),
.K5(K32[5]),

.step5_end(step5_end),
.P0(P33[0]),
.P1(P33[1]),
.P2(P33[2]),
.P3(P33[3]),
.P4(P33[4]),
.P5(P33[5]),
.P6(P33[6]),
.P7(P33[7]),
.P8(P33[8])
);


endmodule

Hi ,

Please find attached file with error corrected.
I have corrected the error only;
Some reg/wire got assigned to remove the error please assign correct value where require.