![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
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Open source VHDL linter
by Unknown on Dec 30, 2004 |
Not available! | ||
Has anyone run across an open source VHDL linter?
Scott Morris
Senior Research Engineer
Battelle Pacific Northwest National Laboratory http://www.pnl.gov/>
PO Box 999
MS P8-20
Richland, WA 99352
Phone: 509-376-3860
Fax: 509-376-3269
Email: morris.scott at pnl.gov morris.scott at pnl.gov>
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Open source VHDL linter
by Unknown on Dec 31, 2004 |
Not available! | ||
Has anyone run across an open source VHDL linter?
Scott Morris
Senior Research Engineer
Email: morris.scott at pnl.gov morris.scott at pnl.gov>
I recall a academic called AMICAL (at a later time it was renamed to ARDID). It claimed to have linting features and could perform rule-checking for synthesis and some other stuff. Maybe the authors of ARDID may provide a version of the tool or the linting engine. Nikolaos Kavvadias Ph.D. Student |
![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
![no use](https://cdn.opencores.org/img/pils_rt.png)