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SystemC design flow
by Unknown on Dec 28, 2003 |
Not available! | ||
Hi guys,
I'd like to know if there is some possibility to build
up a design flow starting from a synthetizable SystemC
source, and without the need of using a Synopsys license.
AFAIK the only synthesis tool that accepts SystemC as
an input (following the rules stated in the "Describing
Synthesizable RTL in SystemC" document available from
Synopsys) is Behavioral Compiler (still from Synopsys),
but I suspect that its license fee is quite expensive for
non-commercial purposes.
BTW, some time ago an academic version of BC was freely
downloadable from Synopsys web site, but I can't find it
anymore.
Days ago I've found a post from Sumit Gupta about a tool
called SPARK that lets you transform ANSI C into VHDL, but
I had a look and I didn't like it so much; a converter
from SystemC to VHDL should be very useful because I
should be able to convert from SystemC to VHDL and then
to synthetize the VHDL using an open tool like Alliance.
Thank you in advance for your suggestions,
Fabrizio
--
=============================================
Fabrizio Fazzino, IT Engineer
fabrizio at fazzino.it - http://www.fazzino.it
=============================================
|
SystemC design flow
by Billditt on Dec 28, 2003 |
Billditt
Posts: 4 Joined: Feb 12, 2002 Last seen: Aug 1, 2021 |
||
There is a SPARK C-to-VHDL tool:
http://www.cecs.uci.edu/~spark
They provide a binary release for download. You would generate VHDL
which would be synthesized, using whatever synthesizer you had.
I have used SystemC for two projects, the latter a pipelined, fixed point
dual harvard architecture processor (For DSP apps). We used SystemC
to model the architecture, to build an RTL testbench and to verify
the RTL using the above (we also used Random Verification via the SVL). We
didnt go all the way to RTL since we already
had fine RTL coders and synthesis tools. But it could be done.
We provided communications between the SystemC reference model and
the RTL simulator via an FLI. Nowadays, just about everyone allows you to
compile SystemC directly into the simulator. You can mix and match behavioural
and RTL descriptions in Verilog, VHDL, and SystemC.
A colleague and I wrote a paper for DVCON outlining this process. It all
turned out
very nicely.
ditt
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SystemC design flow
by Unknown on Dec 28, 2003 |
Not available! | ||
Fabrizio
Did you do any analysis of the SPARK tool ? We are also trying to
evaluate this tool and are trying to figure out if it is even good for
C models - converting synthesizable SystemC to C should not be that
hard. Also, the SPARK tool guys are planning to provide SystemC
support in the future.
What was your analysis of the SPARK tool ?
GG
----- Original Message -----
From: Fabrizio Fazzino fabrizio at f... >
To: cores at o...
Date: Sun, 28 Dec 2003 17:38:24 +0100
Subject: [oc] SystemC design flow
Hi guys,
I'd like to know if there is some possibility to build
up a design flow starting from a synthetizable SystemC
source, and without the need of using a Synopsys license.
AFAIK the only synthesis tool that accepts SystemC as
an input (following the rules stated in the "Describing
Synthesizable RTL in SystemC" document available from
Synopsys) is Behavioral Compiler (still from Synopsys),
but I suspect that its license fee is quite expensive for
non-commercial purposes.
BTW, some time ago an academic version of BC was freely
downloadable from Synopsys web site, but I can't find it
anymore.
Days ago I've found a post from Sumit Gupta about a tool
called SPARK that lets you transform ANSI C into VHDL, but
I had a look and I didn't like it so much; a converter
from SystemC to VHDL should be very useful because I
should be able to convert from SystemC to VHDL and then
to synthetize the VHDL using an open tool like Alliance.
Thank you in advance for your suggestions,
Fabrizio
--
=============================================
Fabrizio Fazzino, IT Engineer
fabrizio at f... - http://www.fazzino.it
=============================================
|
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