Hi, my good friends:

I,a freshman, downloaded a spi master core some days ago. But when I use it, I discovered that I can use the 8bits oc8051 to visit the spi master core via the 32bits wishbone bus. what shall I do to solve this proprom. Thank you.

You have to be much more specific what your problem really is. What "SPI master core" are you referring to? You can (??) use the 8051 core to access the SPI device? So where's the problem? Assuming that you cannot, then your problem seems to be bus-related, but then has nothing to do with the SPI device proper.

Hellwig

Exactly what SPI core are you referring to? If you instantiate the spi_master.vhd from the SPI_MASTER_SLAVE project ( http://opencores.org/project,spi_master_slave ), the system interface is a generic parallel access port. It can be interfaced to a Wishbone bus, if you look at it as a standard register-like interface. You can place a FIFO between the bus and the spi_master port (recommended), to achieve seamless streaming of high-speed SPI decoupled from the bus latency.

- Jonny