OpenCores
First Prev 2/2 no use no use
RE: IP Open-Can
by SJA1000mstr on Jul 31, 2012
SJA1000mstr
Posts: 11
Joined: Jul 18, 2012
Last seen: Jul 31, 2012
Please Mr Mohor,

What is the signal "fifo_selected" supposed to do ? because in your IP et is not linked?

Thank you

SJA1000mstr
RE: IP Open-Can
by Fifo on Aug 10, 2012
Fifo
Posts: 1
Joined: Aug 10, 2012
Last seen: Sep 10, 2012
Hello from Germany, (please excuse my bad english).

Im not familar with open can ip or with philips but i ran into the same problem with an Atmel CAN processor. This processor is using arbitration and error detection (i guess open can ip and phillips, too). This means if TX is going to LOW signal, then RX should be LOW, too. Same with HIGH signal. If TX is not the same as RX, then the controller is generating an error because it thinks that another device on bus has sent out anything else at the same time and has falsified the signal.

I see on your screenshot that RX is always HIGH, so the arbitration and error detection cannot work. Error signals appears 1ms after TX is gone to LOW.

If arbitration error is the reason, then you could test it by connecting RX and TX signal together (just for simulation). After this you should see on scope that at least the target-can-adress will be sent out from your master.

If you are successfully, then this was just the first step only.

Next step:
After successfully sending out the address without arbitration error - the master controller is exepting an ACK signal from target device, but you dont have any targets on simulator. This means the master will stop sending if ACK does not appear on RX - and all you can see is the target adress on TX only - not more and not less. This is the reason why everybody says that you need second device on your can bus to complete the communication.

If you want go further and simulate a complete can transmission, then you could just add second open can core to your project and let it run as slave. So your master will get the ACK signal from slave now. For this you need to connect all TX and RX signals to one bus together (but TX as open drain only).

If your open can ip is not using arbitration error detection, then just forget, what i wrote :c)

Good luck...
First Prev 2/2 no use no use
© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.