Hi,

We are currently working to set up a CAN communication using the Open Can IP.

We successfully wrote and read all IP registers, but when it comes to transmit a message, we only send an error frame, and the error status is activated (see picture).

Does anybody know something about this issue?

Thank you for your answers

SJA1000mstr

Yes, the author knows.
It is called RTFM.

Regards,
Igor

I have been reading it for hours, but I read the SJA1000 datasheet, and the IP is not the SJA1000 itself, there is no datasheet for the IP.

All the registers seem to be filled with good values, but when the transmission begins, there is only error frames.

Thank you for your help,

SJA1000mstr

(And when I say hours I mean weeks...)

My question is not obvious, if someone has a real aswer to offer, please...

Regards,

SJA1000mstr

Are you simulating de Ip Core or your test is in hardware?.

sorry, I didn't see your attached image.
How is your testbench?. How do you connect tx and rx signals?. For a sucesfully simulation you need model the CAN bus transceiver.

I will try, thank you for your answer.
Unfortunately, I simulated it to be able to modify things more easily but the result is exactly the same with the system linked to a transceiver and a CAN Bus...

Regards,

SJA1000mstr

Are you using the proper termination on your transceiver so that the bus is biased into the recessive state? Also, you will need two CAN nodes on the system so that an ACK is generated in the ACK slot, otherwise the transmitter will keep retrying.

Hello,

Could you tell me wich manual you are talking about please? I would be glad to have more informations about the IP, since you are the author.

Regards,

SJA1000mstr

First of all the CAN standard (from Bosch), them the SJA1000 from NXP.

If you want to simulate anything, you should have at least two CANs connected
because one should always reply to the traffic. If you have only one, whatever
you transmit will cause errors.

I understand that we need two nodes when it comes to the real system, but when you simulate a transmission, shouldn't the tx output take the values written in the registers tx_data0...txdata2 ?
because if the values on IP inputs are good, there is no reason why an output shouldn't react properly? and I don't see any answer needed on rx before acknowledge, so tx should send the frame until acknoledge, and then there would be an error. Am I right?

Thank you again for your time.

SJA1000mstr

up please...

Hello again,

I was looking at Mr Gaisler's translation of your code in VHDL, and I saw in the can_bsp.vhd some lines I can't find in your IP (cf attachement).

Moreover, in the RTL view, a signal called "fifo_selected" is linked to nothing. I wonder if the problem comes from that.
When I send data there are only error frames, and when I receive data, an acknowledge is sent but nothing is written in the receive_data_registers...

Anyone can help me please?

sja1000mstr

Few facts:
Verilog version (at Opencores): This is the version you want to use.
VHDL version (at Opencores): Old, NOT-up-to-date version. Do NOT use it. It should be removed, but since I'm not the author of the translation, I will not.
VHDL version (Gaisler): I have no idea what this is, who did it and where it is located. Neither I know from which version in Verilog it was translated from. If you want to use it, talk to them.

This is quite cold and does not help me with your version...
My question is : should there be a RAM between the tx_data_0 and tx signal? because there is something missing here.

Thank you again,

sja1000mstr