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wishbone to interface a FPGA to pld
by Unknown on Jan 8, 2005 |
Not available! | ||
Hello,
I'm looking for a (semi high speed,wishbone) interface to interconnect my pld to a fpga, I'm looking for a (semi high speed,low pin count) interface to interconnect my pld to a FPGA. Is there a standard interface for this? That is simple, it fit in a small pld but flexible that I can re-use it for different applications? My solution: A 8 bit synchronic duplex bus. With a simple wishbone protocol. But I donÂ’t like to re-invent the wheel. So is there a standard solution for this? Thanks in advance, Ernst van Spronsen |
![no use](https://cdn.opencores.org/img/pils_lt.png)
![no use](https://cdn.opencores.org/img/pil_lt.png)
![no use](https://cdn.opencores.org/img/pil_rt.png)
![no use](https://cdn.opencores.org/img/pils_rt.png)