Hi, we have an older Xess XSV development board with a Xilinx Virtex XCV800 FPGA. We are no longer using this board, and would like to donate to a good cause, preferably to some project going on at OpenCores So if you are developing a free IP core, drop me a line, or post to the group ... or if somebody has a good suggestion who should get it ... you must convince me that you are a serious developer though ... ;*) Cheers, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis

Any takers ? -------- Forwarded Message -------- From: Rudolf Usselmann rudi at asics.ws> Hi, we have an older Xess XSV development board with a Xilinx Virtex XCV800 FPGA. We are no longer using this board, and would like to donate to a good cause, preferably to some project going on at OpenCores So if you are developing a free IP core, drop me a line, or post to the group ... or if somebody has a good suggestion who should get it ... you must convince me that you are a serious developer though ... ;*) Cheers, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis

Well if you insist. We (I) am developping a WISHBONE compatible MIPS(ish) CPU. It supports the same subset of instructions as the Plasma Core. The major difference is my design makes use of a 5 stage pipeline with forwarding and minimal amount of hazard detection. I'm also going to realease an improved gcc based toolchain for patent free MIPS CPUs (basically it's nonmips.sourceforge.net), mixed in with a newer version of uClibc all compiled through its newer buildroot makefile system. I've also integrated XIPTECH's ELF2FLT port so that the toolchain can produce flat binaries. To be quite honnest, I doubt my project will ever become production quality, but hopefully it will serve as a example on how to make effective use of VHDL record types in designs, how to describe WISHBONE master and slave devices in VHDL (so far we have the CPU as a master, an SDRAM controller, Flash memory, and some generic slaves that implement wait states, some simple switches), how to deal with pipeline stalls or INOUT pins on FPGAs. We will also be producing a considerable amount of documentation to go along with all this. Anyways, if this meets your criteria, let me know, I'll zip you up a snapshot of the code. Edmond On Fri, 21 Jan 2005 21:24:49 +0700, Rudolf Usselmann rudi at asics.ws> wrote:

On Fri, 2005-01-21 at 21:24 +0700, Rudolf Usselmann wrote:
I was really surprised by the lack of interest in free equipment. Perhaps I was expecting to much ? Anyway, after looking through the hand full of email I got, I decided that the best use for this board would be at: "Dept. of Design and Diagnostics of Digital Systems of Slovak Academy of Sciences" submitted by Martin Simlastik. Martin, please email me you shipping address (privately) and I will get the board out to you. I wouldn't mind even to buy development board and donate them to really cool projects. So if you do start a something unique and interesting in the Free IP Core area, shoot me an email, and I might go and buy a development board for your project. Cheers, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis