My vhdl description of the controller/decoder: http://pastebin.com/Uyhk3NU6

I'm simulating and testing at the moment, only problem is it's a pain to test and i'm getting some odd results in ISIM,

Anyone got any tips to improve the description?
Or even a better way to describe the controller/decoder?

At the moment it's a state machine with 280 states.
I also think that it was using one hot encoding and so my state registers were 280 bits, surely there's a more efficient way.

Hi,

You should post on a more generic forum: http://www.edaboard.com/forum30.html for example.

Franck.