few doubts regarding WISHBONE registered feedback cycle type.
WISHBONE master places a read command during first cycle.
Is it necessary that master should accept the data during second
cycle ?
Can the master insert a wait state by deasserting strobe ?
In that case will the slave come back with data during third cycle ?
can anyone help..?

Thanks in advance
ambili

You're not having doubts, you're asking a question.


The master MUST accept the data when the master asserts CYC, STB, and the
slave asserts ACK.


IF the master negates STB, it will effectively insert wait states.
Note that the master probably shouldn't negate STB in the middle of a
transfer. It should do so at the start of a transfer.
For clearification, a transfer is defined as a single transfer of data
(stb->ack), a burst consists of multiple transfers.


Could be yes. It all depends on the master and the slave.
Please read the spec and try to follow the examples.

Cheers,
Richard