Dear All,

I'm trying to simulate the A VHDL 16550 UART core from the projects and found some files are missing
in the zip file the link from where i had downloaded the project is http://opencores.org/project,a_vhd_16550_uart

The project status says its complete and stable but the files listed below are missing in it.

1. gh_edge_det.vhd
2. gh_register_ce.vhd
3. gh_DECODE_3to8.vhd
4. gh_jkff.vhd
5. gh_baud_rate_gen.vhd
6. gh_counter_down_ce_ld_tc.vhd
7. gh_edge_det_XCD.vhd

I request if some one has these file and test bench to simulate the UART code to please share it across.

Thanks & Best Regards,
Chetan.

read the documentation carefully.
HINT: the beginning of the second chapter

Hi rozpruwacz,

I didn't understand what you meant, below are the lines from the second chapter of the document
(There is only one document in the SVN).

"Until the document is done (and perhaps later as well), those interested in understanding the UART better
should consult the data sheets for the PC16550D.

The gh_vhdl_library (another www.opencores.org project- version 3.17 or later) is used extensively in
this project, and needs to be downloaded separately."

It has nothing to do with the missing files, can you elaborate on what you meant???

Thanks.

Dear All,

I got complete set of missing files of the "a VHDL 16550 UART core" project, one of my friend had sent me these files.

I'm simulating the core step by step and the first thing i did is to set the clocks of modules and configure it with
basic configuration with Baud rate as 9600, 8 Bits, No Parity, 1 Stop Bit and FIFO enabled (by default it will be set),
so below is the register configuration i came up to configure the UART module.

No - Address - Data - Read / Write - Function
1. --- 001 --- 0x00 --- Write ----- Disable Interrupt Enable Register (IER).
2. --- 011 --- 0x80 --- Write ----- Set DLAB Bit in Line Control Register (LCR).
3. 000 Baud Low Byte Write Divisor Latch LSB.
4. 001 Baud High Byte Write Divisor Latch MSB.
5. 011 0x03 Write Clear DLAB Bit in the LCR and set UART parameters as 8 Bits, No Parity & 1 Stop Bit.
6. 010 0x00 Write Set FIFO Control Register (FCR) to Enable FIFO's
7. 011 Read Read back the LCR Register to confirm configuration.
8. 010 Read Read back the FCR Register to confirm configuration.
9. 011 0x80 Write Set DLAB Bit in Line Control Register (LCR).
10. 000 Baud Low Byte Read Divisor Latch LSB to confirm configuration.
11. 001 Baud High Byte Read Divisor Latch MSB to confirm configuration.
12. 011 0x03 Write Clear DLAB Bit in the LCR and set UART parameters as 8 Bits, No Parity & 1 Stop Bit.

Clocks settings:
1. I/P Clock (clk) is of 50 MHz.
2. Baud rate generator clock (BR_clk)is of 1.8432 MHz.

The Issue im facing is that after the configuration the serial data (0xAA) is feed on the input "sRX" pin @ 9600 baud rate
with Start (0) and stop (1) bits embedded to it and this data is suppose to be on "RD" data bus with "RXRDYn" pin high this is not happening.

can any one could help me whether anything else need to be configured or where im going wrong.

Thanks & Best Regards,
Chetan.

This sentence has nothing to do with missing files ?? It exactly says what you must to do to get these files :) You have to download gh_vhdl_library from www.opencores.org.

You have not specified what are the values of DLL and DLM registers. Should be: DLL = 12, DLM = 0. The rest looks fine.

PS. Maybe your friend sent you wrong files :P