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Memory Model in Verilog
by karthikmc on Jan 20, 2005 |
karthikmc
Posts: 1 Joined: Mar 26, 2009 Last seen: Feb 13, 2025 |
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Hello Everyone,
this is my first message to the forum. I am a student working on a digital design which requires a 256 * 8 bit memory. The functionality I require is as follows. 1> the location addressed by the 8 bit address should be checked for its contents. 2> every time a particular location is addressed, its contents should be incremented by a specific step (say one). I know it is a pretty straightforward code in verilog, but I am finding the (almost)simultaneous read-write hard to code, since I am quite new to the nuances of verilog. I would request the members of the forum to please suggest methods to code the above memory model. Regards, Karthik |
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Memory Model in Verilog
by Unknown on Jan 21, 2005 |
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It's actually not that straightforwards if you want it to be real HDL
code. It's three operations (read from memory, increment, write back to memory), and you have to make it look like one operation to the outside world. If you have certain guarentees (like you'll only get one request every 3 or more clock cycles), it's easy; if you need to read more often that than, you have to deal with write-after-read hazards. - Guy |
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Memory Model in Verilog
by Unknown on Jan 25, 2005 |
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Hello,
The problem is not defined well enough to give you the right solution.
I will make some assumptions,
1. This is a RAM model, not the actual design of the RAM, it is not
synthesizable.
2. The RAM must be initialized somehow, you can either write to it, or
you can use a reset. I will use a reset.
3. The control signals for your RAM are (Address, Read, Write, Data_in,
reset, Data_out);
4. This model I am typing in quickly, good code uses comments, and
more structure, you should add them.
5. Data_out will be "XX" during reset and Write and !Read. There are a
lot of options here.
6. Synthesizable RAMS (register files) usually use a clock signal. It is
easier to implement.
module ram_model (Address,Read,Write,Data_in,reset,Data_out);
input [7:0] Address;
input Read,Write,reset;
input [7:0] Data_in;
output [7:0] Data_out;
reg [7:0] RAM[255:0];
reg [7:0] Data_out;
integer i;
always @(Data_in or Address or Write or Read or reset)
begin
if (reset)
begin
for (i=0;ikarthikmc at g...karthikmc at g...>
To:
Date: Thu Jan 20 21:11:29 CET 2005
Subject: [oc] Memory Model in Verilog
Hello Everyone,
this is my first message to the forum. I am a student working on a digital design which requires a 256 * 8 bit memory. The functionality I require is as follows. 1> the location addressed by the 8 bit address should be checked for its contents. 2> every time a particular location is addressed, its contents should be incremented by a specific step (say one). I know it is a pretty straightforward code in verilog, but I am finding the (almost)simultaneous read-write hard to code, since I am quite new to the nuances of verilog. I would request the members of the forum to please suggest methods to code the above memory model. Regards, Karthik |
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