Hi. I downloaded the Intel 8051 Verilog Code from this website.
Link: http://opencores.org/project,8051

The file was in .rar format and I extracted it. After extraction I have 4 folders namely branches, tags, trunks and web_uploads. Folder 'tag' has sub folders like rel_1, rel_2. Similarly folder 'trunks' has sub folders like rtl, bench, sim etc.

I don't know what these folders mean and where the actual verilog files are. I also need to implement this core into an FPGA. I don't know how to proceed from here.

Please help. Thanks

P.S. Am a newbie with programming.

Hello,you could use these files rebuilr a project,use the top file's name as the project name,and then ...enjoy

./trunks/ should contain the latest rtl release.

what would be the top module???what should i write in the top module feild?

what should be my top module feild??

oc8051_top will be in your top level file which you will connect to the physical chips like memory and serial ports etc of the development kit you are using. look at an example top level file of your development kit for a starting point.

i am getting these errors while synthesis.what should i do??


ERROR:HDLCompilers:27 - "../../Documents and Settings/deepak/Desktop/8051/trunk/rtl/verilog/oc8051_alu_test.v" line 62 Illegal redeclaration of 'oc8051_alu'

ERROR:HDLCompilers:26 - "../../Documents and Settings/deepak/Desktop/8051/trunk/rtl/verilog/oc8051_alu_test.v" line 322 Macro reference `OC8051_ALU_PCS is not defined

ERROR:HDLCompilers:27 - "../../Documents and Settings/deepak/Desktop/8051/trunk/rtl/verilog/oc8051_alu_test.v" line 62 Illegal redeclaration of 'oc8051_alu'
ERROR:HDLCompilers:26 - "../../Documents and Settings/deepak/Desktop/8051/trunk/rtl/verilog/oc8051_alu_test.v" line 322 Macro reference `OC8051_ALU_PCS is not defined


i am getting these errors while synthesising!what should i do??

oc8051_alu_test.v is for simulation only.
it is a test bench, you cannot synthesis this module.
just run the simulation only

oc8051_top will be in your top level file which you will connect to the physical chips like memory and serial ports etc of the development kit you are using. look at an example top level file of your development kit for a starting point.

i tried to simulate the top module file but it is showing some errors??
is this file ment for simulation or synthesis?

Hi, I beginner in this work too. I dowloaded this project from here and I am trying with it. How are you progress? I want join forces.

someone have synthesized core 8051?

Hello, I have download code but I couldn't open , which program is used to open code I did with notepad

ActiveHDL