I have to make a triangular signal (from 10Hz to 1MHz) using PWM. All this should be made using HDL Active program and verilog language. I have no idea how to do this, can any one help me with this?

http://www.alteraforum.com/forum/showthread.php?t=4574

and

http://www.scribd.com/doc/64356987/HDL-Lab-Manual (page 54)

hi friend,

I understood your question as :
You want to generate triangular wave between 1000nsec to 10^8 nsec, remaining all the time it should be 0.

NOTE : You can't generate analog signals using verilog. Verilog is only for digital
signals.

So develop a up-down counter, maintain upper limit of counter as maximum amplitude of triangular wave (similarly for lower limit). Now give this signal to Digital to analog convertor(DAC) you will get triangular wave as output.

Steps to generate up-down counter.

step1: take a clock whose time period is multiple of 1000 (ex. T=10nsec)

step2: at 100thposedge make counter value to 1 then 2 then so on...keeps it increasing. Once the upper limit is reached then make it decreasing(you have to use 1 flag variable(1-bit) to change the counting direction). Like that it will continue till 10^7thposedge is reached.

step3: at 10^7thposedge make count output 0.


I hope you got it. For any clarification please feel free to contact. I will glad to answer.

----Sudhanshu Billore

if you can't add DAC chip into your design, or if it's not present on your FPGA kit, then you can make simple PWM DAC using logic and filter it with simple RC lowpass filter
your input is signal waveform data, for example your triangle...
basically everything from previous post with suggestions apply...
so you already have numbers... like 0 15 31 47 63 47 31 15 ... which makes triagle,
in this example maximum value is 63, min is 0, this is coded in 6 bits

PWM stage will output one bit signal, which when filtered (with lowpass) will look like analog signal... the higher value goes into PWM stage, the larger output voltage will be
for one PWM period you take one input number, for example 31... 31 is like one half of maximum output analog voltage and you have to output
logical ones for cca half time of period, which gives some charge to RC filter - analog voltage builds up, then for other half time you start output zeores, voltage gets drained from RC filter into ground with FPGA output pin... in average and with more PWM periods this looks like quite smooth analog signal

simple implementation:
make up counter that counts one PWM period, up counter has the same amount of bits as input data
compare input data with value of up counter... if the counter has smaller value than data make PWM output logical one
if you have larger or equal value than data, then output logical zero
if your data have 8 bits, then clock for PWM period counter should be 2^8=256 times faster than speed of generating the data

so for max. voltage input data in my example is 63 ... counter will have values 0, 1, 2 ... which will be for most time smaller than 63 on input, so output signal will be mostly always on = at max voltage.
for input 0 comparator will always output zero and your signal will be always 0V.

RC filter has to have cut off frequency larger than frequency of your triangle wave. I'm not sure how to calculate it exactly, triangle has higher harmonic frequencies that should not be cut off.