Hi,

if someone is still looking for a configurable FFT co-processor then have a look at
http://sourceforge.net/projects/belfft/
bel_fft is written in Verilog, comes along with a graphical configuration Java wizard,
supports different bus interfaces (AXI, Wishbone, Avalon), has a simulation environment,
some software examples and is distributed under GNU LGPL 2.1. It aims to be a hardware
replacement of the software FFT implementation Kiss.
The core is still under development, so any feedback is welcome!

Best regards,
Frank

Hi,

there is now an update available (0.7). Some bugs were fixed and the Xilinx Vivado IP-Integrator is supported now. In addition two complete example designs for Xilinx EDK and Vivado are included, connecting the FFT co-processor to the ACP port of the processor system of the Xilinx Zynq devices.
There were also some fixes of the Wishbone interface.

Best regards,
Frank