Hi,
I have been reading the Wishbone B4 specifications and I don't understand the incrementing burst cycle.

Illustration 4-10 shows a 4-beat wrapped incrementing burst for a 32 bit data array. In the illustration we can see four accesses, from address N to address N+C. My question is: Why four accesses? Is this number fix for a 32 bit data array? Can I do a different number of accesses?

In other words, is the number of accesses dependent on the size of the data array? How can I do different number of accesses? For example using incrementing burst to access to 100 adresses with a 32 bits data array.

Best regards

Hi,

You can do any number of accesses. It keeps going until you set cti = '111'. So to read 100 addresses, you need to set bte to '00' (for linear burst) and send 99 transactions with cti='010' and then a final transaction with cti = '111'

Side note: It seems like you got confused by the text in 4.4.4. What it says is that if you have a 32 bit data bus (4 bytes), the address will be incremented by four on every access

Hope this helps,

--
Olof Kindgren
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ORSoC
Website: www.orsoc.se
Email: olof.kindgren@orsoc.se
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FPGA, ASIC, DSP - embedded SoC design