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Free Place & Route
by Unknown on Jan 31, 2005 |
Not available! | ||
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----- Original Message -----
From: antti at c...
To: tom at l..., cores at o...
Date: Sun, 7 Sep 2003 12:36:09 +0200
Subject: Re: [oc] Free Place & Route
> I would focus on a small part of the flow, then work outwards.
The
> following illustrates the Xilinx flow from RTL to bit file:
> > 1. Synthesis : HDL -> EDIF > 2. NGDBuild : EDIF/UCF -> NGD > 3. MAP : NGD -> NCD > 4. PAR : NCD -> NCD > 5. BitGen : NCD -> BIT > > The approach I would take would be to first tackle step 4, followed
> by 3 and 2. Are NGD and NCD proprietary formats?
YES. Xilinx prop.
NCD is simple binary record structure
NGD (and other NG*) are compressed and/or DES encrypted.
there is also XDL format (what I did not know until today)
I guess XDL can be converted to bitstream, but XDL is
described so coulc be produced by 3rd party generator.
hmm XDL see here, not quite that but also useful info :)
http://opencollector.org/news/Bitstream/suggestions.shtml
***
Xdl is a single tool with 3 fundamental modes:
* Report Device Resource Information
* Convert NCD to XDL (ncd2xdl)
* Convert XDL to NCD (xdl2ncd)
Report generates a report of the physical resources
available for a specific part.
Ncd2xdl reads in an NCD file and generates an ASCII XDL file.
Xdl2ncd reads in an XDL file and generates an NCD file.
XDL is also a fully featured Physical Design language that
provides direct read and write access to Xilinx's proprietary
Native Circuit Description (NCD). This access enables all
users to write tools to address their individual FPGA
design needs.
***
> Proposed Simplified First Round Specs:
> - Accept a configuration file for a Virtex2/Spartan3 part. > - Consume pre PAR NCD file. > - Produce post PAR NCD file. > > Tom |
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