Hello friends...
i am doing project on RISC architecture using verilog .I need help in understanding the working of these two which is marked in figure.


please help me guys....

Hello,

I will check this later for you if you want just to be sure.
but my initial thoughts are like this::

the small block on the right (outa_s1) is basically a forwarding technique or some sort of a branch prediction.
when you have a branch command (such as jump - (if else)) then the result of the branch is only known at the end of the execution unit and even at WRITEBACK block sometimes. (execution unit is the unit with the ALU and the opA,opB,Offset. and the WRIETEBACK is the ALU out).
Now that outA_s1 unit is basically a comparision unit that makes it easier to know if the branch is taken or not take and the result is propagated back.

the big block to the left is the instruction decode unit.
the command is read from the memory (such as ADD op1, op2 or in case of 3 operands then ADD op1, op2, op3).
if the instruction is of type CMD op1,op2 then write_s2 and read_s2 are the same register.
the sign Ext. is (SIGN EXTENTION), this is used to LOAD,STORE commands incase ur loading/storing a negative number - compliment of 2). pay attention that the sign-ext8_s2 is also connected to the offset block (below OpB).

I hope this helps you.. if someone disagree with me then ill be happy to revise my MIPS architecture schematics.