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conditional compilation in VHDL by Unknown on Feb 1, 2005			Not available!
Maybe a bit too late ;-) , but you could check out EVHDL on www.entner-electronics.com (download-section). It basically implements a C-like preprocessor for VHDL. Regards, Thomas ----- Original Message ----- From: <A HREF="http://www.opencores.org/mailman/listinfo/cores">unni_cv at h...</A> To: <A HREF="http://www.opencores.org/mailman/listinfo/cores">cores at o...</A> Date: Thu, 25 Jul 2002 14:15:15 -0100 Subject: [oc] conditional compilation in VHDL [q] Hi, Is there any conditional compilation switches in VHDL, like the `ifdef in verilog? We can use generic and generate statemenst to emulate `ifdef to an extend, but I think the flexibility is less. I wonder if there si any? I haven't come across yet? unni [/q] Maybe a bit too late ;-) , but you could check out EVHDL on www.entner-electronics.com (download-section). It basically implements a C-like preprocessor for VHDL. Regards, Thomas ----- Original Message ----- From: unni_cv at h... To: cores at o... Date: Thu, 25 Jul 2002 14:15:15 -0100 Subject: [oc] conditional compilation in VHDL Hi, Is there any conditional compilation switches in VHDL, like the `ifdef in verilog? We can use generic and generate statemenst to emulate `ifdef to an extend, but I think the flexibility is less. I wonder if there si any? I haven't come across yet? unni

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