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FPGA to ASIC
by badmanjoe on Apr 14, 2013 		badmanjoe
Posts: 34
Joined: Aug 16, 2012
Last seen: Oct 9, 2014
Hi guys,

I have a design running on an FPGA board.
What are the steps that i need to take to convert my design from FPGA to ASIC?

thank you
RE: FPGA to ASIC
by MarcAlexandre on Apr 14, 2013 		MarcAlexandre
Posts: 1
Joined: Jul 17, 2012
Last seen: Dec 10, 2024
Hi,

For doing that you can use Rtl compiler and SoC Encounter (Velocity) from Cadence. Rtl compiler allow you to have a Netlist with timing requirement met using your Rtl files and your SDC. SoC Encounter uses this Netlist and physical cells libraries and gives you your ASIC design as a GDSII file.

Hope it will help you.
RE: FPGA to ASIC
by kenpillay on Apr 15, 2013 		kenpillay
Posts: 2
Joined: Feb 28, 2013
Last seen: Jun 9, 2015
http://opencircuitdesign.com/qflow/index.html
RE: FPGA to ASIC
by badmanjoe on Apr 15, 2013 		badmanjoe
Posts: 34
Joined: Aug 16, 2012
Last seen: Oct 9, 2014
Thank you for the quick reply! Very helpful!
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