Anyone familiar with doing a single byte write and a single byte read using an I2C controller?

I have some code written so far and will post it if I can get some assistance

This is what I'm working on at the moment:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY Lab3 IS
GENERIC(
input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
PORT(
clk : IN STD_LOGIC;
reset_n : IN STD_LOGIC;
we : IN STD_LOGIC;
address : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
rd : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
I2C_SCLK : OUT STD_LOGIC;
Read_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
I2C_SDAT : INOUT STD_LOGIC);
END Lab3;

ARCHITECTURE logic OF Lab3 IS
CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
TYPE machine IS(ready, start, command, slv_ack1, wr, rdd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --clock edges for I2C_SDAT
SIGNAL scl_clk : STD_LOGIC;
SIGNAL scl_ena : STD_LOGIC := '0';
SIGNAL sda_int : STD_LOGIC := '1';
SIGNAL sda_ena_n : STD_LOGIC;
SIGNAL address_rd : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL data_tx : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL data_rx : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7;
SIGNAL stretch : STD_LOGIC := '0';
BEGIN

--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
IF(count = divider*4-1) THEN
count := 0;
ELSIF(stretch = '0') THEN
count := count + 1;
END IF;
CASE count IS
WHEN 0 TO divider-1 =>
scl_clk data_clk WHEN divider TO divider*2-1 =>
scl_clk data_clk -- WHEN divider*2 TO divider*3-1 =>
-- scl_clk -- IF(scl = '0') THEN
-- stretch -- ELSE
-- stretch -- END IF;
-- data_clk WHEN OTHERS => --last 1/4 cycle of clocking
scl_clk data_clk END CASE;
END IF;
END PROCESS;

--state machine and writing to I2C_SDAT during scl low (data_clk rising edge)
PROCESS(data_clk, reset_n)
BEGIN
IF(reset_n = '0') THEN
state I2C_SCLK scl_ena sda_int bit_cnt Read_data ELSIF(data_clk'EVENT AND data_clk = '1') THEN
CASE state IS
WHEN ready =>
IF(we = '1') THEN
I2C_SCLK address_rd data_tx state ELSE
I2C_SCLK state END IF;
WHEN start =>
I2C_SCLK scl_ena sda_int state

WHEN command =>
IF(bit_cnt = 0) THEN
sda_int bit_cnt state ELSE
bit_cnt sda_int state END IF;
WHEN slv_ack1 =>
IF(address_rd(0) = '0') THEN
sda_int state ELSE
sda_int state END IF;
WHEN wr =>
I2C_SCLK IF(bit_cnt = 0) THEN
sda_int bit_cnt state ELSE
bit_cnt sda_int state END IF;
WHEN rdd =>
I2C_SCLK IF(bit_cnt = 0) THEN
IF(we = '1' AND rd = '1') THEN
sda_int ELSE
sda_int END IF;
bit_cnt Read_data state ELSE
bit_cnt state END IF;
WHEN slv_ack2 =>
IF(we = '1') THEN
I2C_SCLK address_rd data_tx IF(rd = '1') THEN
state ELSE
sda_int state END IF;
ELSE
scl_ena state END IF;
WHEN mstr_ack =>
IF(we = '1') THEN
I2C_SCLK address_rd data_tx IF(rd = '0') THEN
state ELSE
sda_int state END IF;
ELSE
scl_ena state END IF;
WHEN stop =>
I2C_SCLK state END CASE;
END IF;

--reading from I2C_SDAT during scl high (falling edge of data_clk)
-- IF(reset_n = '0') THEN --reset asserted
-- ack_error -- ELSIF(data_clk'EVENT AND data_clk = '0') THEN
-- CASE state IS
-- WHEN start =>
-- ack_error -- WHEN slv_ack1 =>
-- ack_error -- WHEN rdd =>
-- data_rx(bit_cnt) -- WHEN slv_ack2 =>
-- ack_error -- WHEN OTHERS =>
-- NULL;
-- END CASE;
-- END IF;

END PROCESS;

END logic;

have you ever tried i2c implementation using systemc?

No, I am not familiar with that. I would like to speak to you more in depth. Please send me an email :

paparit432@yahoo.com

2 prabu28
and what synthesis tool you are using for the SystemC sources?

I am using GTK waveform for signal viewing

still looking for some help on my finished code. anyone able to help?