1/1 
|
I2C Core RTL Simulation / FPGA mismatch...
by JeffHanoch on Feb 26, 2005 |
JeffHanoch
Posts: 6 Joined: Jun 9, 2008 Last seen: May 22, 2024 |
||
|
I'm using an FPGA to verify an ASIC which is using the I2C core. I'm
getting a mismatch between the RTL simulation & the actual FPGA gates
when writing to the I2C CR (command register).
I setup the 2 prer bytes with known values. Then when I write the cr
register, the value written to the cr overwrites the prer(7:0). This is
the case only in the FPGA. In rtl simulation, it works as expected.
Upon further examination of the rtl code, I think I have found an issue.
Please correct me if I'm wrong.
Here's the code snippet with the case statement...
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer http://www.opencores.org/forums.cgi/cores/attachments/20050226/fa4df2e5/attachment.pgp
|
|||
|
I2C Core RTL Simulation / FPGA mismatch...
by Unknown on Feb 27, 2005 |
Not available! | ||
|
Hi Jeff,
if (wb_wacc)
case (wb_adr_i) // synopsys full_case parallel_case 3'b000 : prer [ 7:0] 3'b001 : prer [15:8] 3'b010 : ctr 3'b011 : txr endcase Does the // synopsys full_case parallel_case not tell the synthesis tool that ALL the cases are listed? All other cases are considered "don't care" by the synthesis tool, right? Sorta. The "cr" register is mapped at address 3'b100. This case is not listed in the case statment, so this bit is optimized away and is not considered important. That's the problem... now when address 3'b100 is written, the case statement sees it as 3'bx00 and the prer(7:0) is written as well as cr. You're right. I fixed it and uploaded a new version. I also fixed the scl/sda delay issue in the testbench.
Does the case statement not need a default line which keeps
the previous values for the 4 registers? Am I misunderstanding this concept? You either use the full_case statement, or you add a default statement. In this case we need the default statement. Please download the latest version from OpenCores. Cheers, Richard |
|||
1/1