in asynchronous fifo if one clock domain is writing at 100MHz and other clock domain reading at 10MHz, how to synchronize them.

this is nothing to do with clock domain crossing, its you writing data 10 x faster than its being read, what do you imagine is going to happen?
Fifos are not magic, you still need some form of flow control to stop the fifo from becoming full.

2 sunith
besides flow control you will need also gray-counters

There are many possible implementations of an async FIFO. Some use grey counters, some do not. Understand and solve the basic problem of clock domain crossing, first, and proceed from there.

Clifford Cummings wrote a wonderful document on how to do clock domain crossings. I just found it (again) here.

My favorite way of handling crossings across a FIFO is to send a "half-full" wire. You might be successful synchronizing this with a closed loop solution, such as section 4.5 of the document describes. On the other hand, FIFOs tend to be well behaved, so you might find the open loop synchronizer on this half-full wire to be sufficient.

Just some thoughts for you,
Dan