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a bit of newbie advice .. by Unknown on Mar 2, 2005			Not available!
Hi, I'm a bit new to verilog and I have the situation where I want to generate a clock from a clock available on the board, however the ratio is 3.5:1 i.e. I want a 8 MHz clock from a 28MHz clock source. Does anybody have any hint's or pointers in the right direction ? Right now I am thinking of adding a secondary clock source, but I would be glad if I could avoid it :-) . / regards, Lars Segerlund Hi, I'm a bit new to verilog and I have the situation where I want to generate a clock from a clock available on the board, however the ratio is 3.5:1 i.e. I want a 8 MHz clock from a 28MHz clock source. Does anybody have any hint's or pointers in the right direction ? Right now I am thinking of adding a secondary clock source, but I would be glad if I could avoid it :-) . / regards, Lars Segerlund

a bit of newbie advice .. by Unknown on Mar 2, 2005			Not available!
[q] Hi, I'm a bit new to verilog and I have the situation where I want to generate a clock from a clock available on the board, however the ratio is 3.5:1 i.e. I want a 8 MHz clock from a 28MHz clock source. Does anybody have any hint's or pointers in the right direction ? Right now I am thinking of adding a secondary clock source, but I would be glad if I could avoid it :-) . / regards, Lars Segerlund _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A> [/q] Lars, You could do something like this: _ _ _ _ _ _ _ \| \|_\| \|_\| \|_\| \|_\| \|_\| \|_\| \|_ 28MHz clock _______ _______ \| \|_______\| \|___ 8MHz clock (on average) Regards, David. Hi, I'm a bit new to verilog and I have the situation where I want to generate a clock from a clock available on the board, however the ratio is 3.5:1 i.e. I want a 8 MHz clock from a 28MHz clock source. Does anybody have any hint's or pointers in the right direction ? Right now I am thinking of adding a secondary clock source, but I would be glad if I could avoid it :-) . / regards, Lars Segerlund _______________________________________________ http://www.opencores.org/mailman/listinfo/cores Lars, You could do something like this: _ _ _ _ _ _ _ \| \|_\| \|_\| \|_\| \|_\| \|_\| \|_\| \|_ 28MHz clock _______ _______ \| \|_______\| \|___ 8MHz clock (on average) Regards, David.

a bit of newbie advice .. by Unknown on Mar 2, 2005			Not available!
You can achieve this using combinatorial logic with feedback. Basically you need to produce a state machine which changes state on both clock edges but doesn't use clocked registers to achieve this (as most registers will only clock on one edge). In your design you have to very careful about race conditions as they can stop the whole thing from working. If you can do a search on OpenCores (it wasn't working for me) I posted the code for a divide by 1.5 clock I think some time ago. If that isn't enough to get you going then post again and I'll think on your problem some more. It is solvable though. Colin [q] I'm a bit new to verilog and I have the situation where I want to generate a clock from a clock available on the board, however the ratio is 3.5:1 i.e. I want a 8 MHz clock from a 28MHz clock source. Does anybody have any hint's or pointers in the right direction ? Right now I am thinking of adding a secondary clock source, but I would be glad if I could avoid it :-) . / regards, Lars Segerlund[/q] -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.308 / Virus Database: 266.5.7 - Release Date: 01/03/2005 You can achieve this using combinatorial logic with feedback. Basically you need to produce a state machine which changes state on both clock edges but doesn't use clocked registers to achieve this (as most registers will only clock on one edge). In your design you have to very careful about race conditions as they can stop the whole thing from working. If you can do a search on OpenCores (it wasn't working for me) I posted the code for a divide by 1.5 clock I think some time ago. If that isn't enough to get you going then post again and I'll think on your problem some more. It is solvable though. Colin I'm a bit new to verilog and I have the situation where I want to generate a clock from a clock available on the board, however the ratio is 3.5:1 i.e. I want a 8 MHz clock from a 28MHz clock source. Does anybody have any hint's or pointers in the right direction ? Right now I am thinking of adding a secondary clock source, but I would be glad if I could avoid it :-) . / regards, Lars Segerlund -- No virus found in this outgoing message. Checked by AVG Anti-Virus. Version: 7.0.308 / Virus Database: 266.5.7 - Release Date: 01/03/2005

a bit of newbie advice .. by Unknown on Mar 2, 2005			Not available!
On Wed, 2 Mar 2005 17:25:34 +0100, Lars Segerlund <<A HREF="http://www.opencores.org/mailman/listinfo/cores">lars.segerlund at comsys.se</A>> wrote: [q] Hi, I'm a bit new to verilog and I have the situation where I want to generate a clock from a clock available on the board, however the ratio is 3.5:1 i.e. I want a 8 MHz clock from a 28MHz clock source. Does anybody have any hint's or pointers in the right direction ? Right now I am thinking of adding a secondary clock source, but I would be glad if I could avoid it :-) .[/q] One way you could tackle it is to use an on-chip PLL to multiply up your clock source x2 (to 56 Mhz), then create a simple state machine to divide by 7. If you're desiging with something that has built-in PLLs and you're willing to live with a little jitter, it's cleaner than trying to figure out how to create glitch-free combinatorial logic. - Guy On Wed, 2 Mar 2005 17:25:34 +0100, Lars Segerlund lars.segerlund at comsys.se> wrote: Hi, I'm a bit new to verilog and I have the situation where I want to generate a clock from a clock available on the board, however the ratio is 3.5:1 i.e. I want a 8 MHz clock from a 28MHz clock source. Does anybody have any hint's or pointers in the right direction ? Right now I am thinking of adding a secondary clock source, but I would be glad if I could avoid it :-) . One way you could tackle it is to use an on-chip PLL to multiply up your clock source x2 (to 56 Mhz), then create a simple state machine to divide by 7. If you're desiging with something that has built-in PLLs and you're willing to live with a little jitter, it's cleaner than trying to figure out how to create glitch-free combinatorial logic. - Guy

a bit of newbie advice .. by Unknown on Mar 2, 2005			Not available!
Hi Lars, Assuming your design has close to a 50% duty cycle on your 28Mhz clock source and your system doesn't care about jitter in the 8Mhz clock you could try something like this... Generate two 4 Mhz clocks by dividing the 28Mhz by 7. One clock is generated on the positive edge of the clock and the other on the negative edge. You would then or the two clocks togethor to generate the 8Mhz clock. Here's some VHDL code that shows my solution... library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity clk28to8 is Port ( clk28 : in std_logic; resetn : in std_logic; clk8 : out std_logic ); end clk28to8; architecture RTL of clk28to8 is signal clk8pos : std_logic; signal clk8neg : std_logic; begin -- Or two outputs to generate clock clk8 <= clk8pos or clk8neg; -- create the positive edge pulse -- This divides the 28 Mhz input by 7 to generate a 4Mhz clock -- The rising edge of the 28 Mhz clock is used process ( clk28, resetn ) variable pos_cnt : unsigned(2 downto 0); begin if resetn = '0' then clk8pos <= '0'; pos_cnt := (others => '0' ); elsif clk28'event and clk28 = '1' then if pos_cnt = 1 or pos_cnt = 2 then pos_cnt := pos_cnt + 1; clk8pos <= '1'; elsif pos_cnt < 6 then pos_cnt := pos_cnt + 1; clk8pos <= '0'; else pos_cnt := (others => '0' ); clk8pos <= '0'; end if; end if; end process; -- create the negative edge pulse -- This divides the 28 Mhz input by 7 to generate a 4Mhz clock -- The falling edge of the 28 Mhz clock is used process ( clk28, resetn ) variable neg_cnt : unsigned(2 downto 0); begin if resetn = '0' then clk8neg <= '0'; neg_cnt := (others => '0' ); elsif clk28'event and clk28 = '0' then -- use the positive clock to sync the negative edge of the clock if clk8pos = '1' then neg_cnt := (others => '0' ); clk8neg <= '0'; elsif neg_cnt = 1 or neg_cnt = 2 then neg_cnt := neg_cnt + 1; clk8neg <= '1'; elsif neg_cnt < 6 then neg_cnt := neg_cnt + 1; clk8neg <= '0'; else neg_cnt := (others => '0' ); clk8neg <= '0'; end if; end if; end process; end RTL; ----- Original Message ----- From: Lars Segerlund<<A HREF="http://www.opencores.org/mailman/listinfo/cores">lars.segerlund at c...</A>> To: Date: Wed Mar 2 17:25:34 CET 2005 Subject: [oc] a bit of newbie advice .. [q] Hi, I'm a bit new to verilog and I have the situation where I want to generate a clock from a clock available on the board, however the ratio is 3.5:1 i.e. I want a 8 MHz clock from a 28MHz clock source. Does anybody have any hint's or pointers in the right direction ? Right now I am thinking of adding a secondary clock source, but I would be glad if I could avoid it :-) . / regards, Lars Segerlund [/q] Hi Lars, Assuming your design has close to a 50% duty cycle on your 28Mhz clock source and your system doesn't care about jitter in the 8Mhz clock you could try something like this... Generate two 4 Mhz clocks by dividing the 28Mhz by 7. One clock is generated on the positive edge of the clock and the other on the negative edge. You would then or the two clocks togethor to generate the 8Mhz clock. Here's some VHDL code that shows my solution... library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity clk28to8 is Port ( clk28 : in std_logic; resetn : in std_logic; clk8 : out std_logic ); end clk28to8; architecture RTL of clk28to8 is signal clk8pos : std_logic; signal clk8neg : std_logic; begin -- Or two outputs to generate clock clk8 '0' ); elsif clk28'event and clk28 = '1' then if pos_cnt = 1 or pos_cnt = 2 then pos_cnt := pos_cnt + 1; clk8pos '0' ); clk8pos '0' ); elsif clk28'event and clk28 = '0' then -- use the positive clock to sync the negative edge of the clock if clk8pos = '1' then neg_cnt := (others => '0' ); clk8neg '0' ); clk8neg lars.segerlund at c...> To: Date: Wed Mar 2 17:25:34 CET 2005 Subject: [oc] a bit of newbie advice .. Hi, I'm a bit new to verilog and I have the situation where I want to generate a clock from a clock available on the board, however the ratio is 3.5:1 i.e. I want a 8 MHz clock from a 28MHz clock source. Does anybody have any hint's or pointers in the right direction ? Right now I am thinking of adding a secondary clock source, but I would be glad if I could avoid it :-) . / regards, Lars Segerlund

a bit of newbie advice .. by Unknown on Mar 4, 2005			Not available!
Thanks again, This does the trick. / regards, Lars Segerlund. On Wed, 2 Mar 2005 22:44:20 +0100 <A HREF="http://www.opencores.org/mailman/listinfo/cores">mrussell at design-group.com</A> wrote: [q] Hi Lars, Assuming your design has close to a 50% duty cycle on your 28Mhz clock source and your system doesn't care about jitter in the 8Mhz clock you could try something like this... Generate two 4 Mhz clocks by dividing the 28Mhz by 7. One clock is generated on the positive edge of the clock and the other on the negative edge. You would then or the two clocks togethor to generate the 8Mhz clock. Here's some VHDL code that shows my solution... library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity clk28to8 is Port ( clk28 : in std_logic; resetn : in std_logic; clk8 : out std_logic ); end clk28to8; architecture RTL of clk28to8 is signal clk8pos : std_logic; signal clk8neg : std_logic; begin -- Or two outputs to generate clock clk8 <= clk8pos or clk8neg; -- create the positive edge pulse -- This divides the 28 Mhz input by 7 to generate a 4Mhz clock -- The rising edge of the 28 Mhz clock is used process ( clk28, resetn ) variable pos_cnt : unsigned(2 downto 0); begin if resetn = '0' then clk8pos <= '0'; pos_cnt := (others => '0' ); elsif clk28'event and clk28 = '1' then if pos_cnt = 1 or pos_cnt = 2 then pos_cnt := pos_cnt + 1; clk8pos <= '1'; elsif pos_cnt < 6 then pos_cnt := pos_cnt + 1; clk8pos <= '0'; else pos_cnt := (others => '0' ); clk8pos <= '0'; end if; end if; end process; -- create the negative edge pulse -- This divides the 28 Mhz input by 7 to generate a 4Mhz clock -- The falling edge of the 28 Mhz clock is used process ( clk28, resetn ) variable neg_cnt : unsigned(2 downto 0); begin if resetn = '0' then clk8neg <= '0'; neg_cnt := (others => '0' ); elsif clk28'event and clk28 = '0' then -- use the positive clock to sync the negative edge of the clock if clk8pos = '1' then neg_cnt := (others => '0' ); clk8neg <= '0'; elsif neg_cnt = 1 or neg_cnt = 2 then neg_cnt := neg_cnt + 1; clk8neg <= '1'; elsif neg_cnt < 6 then neg_cnt := neg_cnt + 1; clk8neg <= '0'; else neg_cnt := (others => '0' ); clk8neg <= '0'; end if; end if; end process; end RTL; ----- Original Message ----- From: Lars Segerlund<<A HREF="http://www.opencores.org/mailman/listinfo/cores">lars.segerlund at c...</A>> To: Date: Wed Mar 2 17:25:34 CET 2005 Subject: [oc] a bit of newbie advice .. [q]> Hi, > I'm a bit new to verilog and I have the situation where I want to > generate a clock > from a clock available on the board, however the ratio is 3.5:1 > i.e. I want a > 8 MHz clock from a 28MHz clock source. > Does anybody have any hint's or pointers in the right direction ? > Right now I am thinking of adding a secondary clock source, but I > would be glad if > I could avoid it :-) . > / regards, Lars Segerlund > > [/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/cores">http://www.opencores.org/mailman/listinfo/cores</A>[/q] Thanks again, This does the trick. / regards, Lars Segerlund. On Wed, 2 Mar 2005 22:44:20 +0100 mrussell at design-group.com wrote: Hi Lars, Assuming your design has close to a 50% duty cycle on your 28Mhz clock source and your system doesn't care about jitter in the 8Mhz clock you could try something like this... Generate two 4 Mhz clocks by dividing the 28Mhz by 7. One clock is generated on the positive edge of the clock and the other on the negative edge. You would then or the two clocks togethor to generate the 8Mhz clock. Here's some VHDL code that shows my solution... library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity clk28to8 is Port ( clk28 : in std_logic; resetn : in std_logic; clk8 : out std_logic ); end clk28to8; architecture RTL of clk28to8 is signal clk8pos : std_logic; signal clk8neg : std_logic; begin -- Or two outputs to generate clock clk8 '0' ); elsif clk28'event and clk28 = '1' then if pos_cnt = 1 or pos_cnt = 2 then pos_cnt := pos_cnt + 1; clk8pos '0' ); clk8pos '0' ); elsif clk28'event and clk28 = '0' then -- use the positive clock to sync the negative edge of the clock if clk8pos = '1' then neg_cnt := (others => '0' ); clk8neg '0' ); clk8neg lars.segerlund at c...> To: Date: Wed Mar 2 17:25:34 CET 2005 Subject: [oc] a bit of newbie advice .. > Hi, > I'm a bit new to verilog and I have the situation where I want to > generate a clock > from a clock available on the board, however the ratio is 3.5:1 > i.e. I want a > 8 MHz clock from a 28MHz clock source. > Does anybody have any hint's or pointers in the right direction ? > Right now I am thinking of adding a secondary clock source, but I > would be glad if > I could avoid it :-) . > / regards, Lars Segerlund > > _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

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