Hi,
I'm new to FPGA and want to program one of AES-related cores hosted on OpenCores (crypto cores) on a Xilinx FPGA but have questions.

can I load a core that targeted to another device on Xilinx XC3S400(PQ208) FPGA ? (I want to bought a header board that have XC3S400(PQ208), and want to evaluate the core with this header board but all the cores or modules that are AES-related targeted to another xilinx FPGA)
can I change the pin definition of the program according to my header board ?
how can I give a digital plain stream to it and give cipher stream ?
Thanks,
Regards.

Yes you can do all those things but you have to remember that the opencores AES implementation is very poor and you will need to modify the code so that it makes use of block ram and so in the whatever fpga you are using. You can change the pin out by modifying the ucf file which is where all the pin definitions are held.
How you get data into it and out of it is very much down to what sort of system you want to attach it to, writing a suitable interface at the top level springs to mind as the best solution. the top level as it currently stands on all the opencore implementations exposes all the key bits and the plain text and cipher text as one big lump so that needs sorting before you can do anything useful with it.

mail me if you get stuck I might help you as Ive rewritten aes to suit my own requirements before so I know all the nasty bugs on the opencores implementations.


jeremy ' at' etdyn.com

Ok, Very Thanks, I go to start this project.

OK, Very Thanks. I go to start this project. May I have your email address ?

Jezmo,I want to use an AES implementation using opencores. Could you give me advice?