Hi,

I am doing a project on audio codec design and am using a Nand Flash memory for storage and i have to design a controller for it. I am using an altera cyclone FPGA and niosII processor and have to interface the avalon MM bus with the ONFI interface for nand flash memory.
As I have no prior experience in Nand flash controller, i am facing difficulty in making the architecture of nand flash controller which involves various blocks like "bad block management" ,"wear leveling", "ECC block","command translation" etc and the reference material for nand flash memory is not much over the internet as it is for SDRAM and SD card controller.
Kindly guide me to some reference material on architecture. , if somebody could provide me some very basic architecture model of the controller or a basic IP core , it would be of great help.


regards,
abhinav