Send Cores mailing list submissions to cores at opencores.org To subscribe or unsubscribe via the World Wide Web, visit http://www.opencores.org/mailman/listinfo/cores or, via email, send a message with subject or body 'help' to cores-request at opencores.org You can reach the person managing the list at cores-owner at opencores.org When replying, please edit your Subject line so it is more specific than "Re: Contents of Cores digest..." Today's Topics: 1. I2C Core RTL Simulation / FPGA mismatch... (Jeff Hanoch) 2. what opensource tools to use (=?gb2312?B?zPrKrw==?=) 3. Re: what opensource tools to use (Mike Delaney) 4. Re: what opensource tools to use (Michael Hordijk) 5. Re: Re: what opensource tools to use (Mike Delaney) 6. RE: I2C Core RTL Simulation / FPGA mismatch... (Richard Herveille) 7. Re: Re: what opensource tools to use (Nikolaos Kavvadias) 8. Re: Re: what opensource tools to use (Mike Delaney) 9. RE: Re: what opensource tools to use (Sheila Carey) ---------------------------------------------------------------------- Message: 1 Date: Fri, 25 Feb 2005 17:05:11 -0600 From: Jeff Hanoch jeff at lowrance.com> Subject: [oc] I2C Core RTL Simulation / FPGA mismatch... To: Opencores cores at opencores.org> Message-ID: 1109372711.4587.52.camel at asic1.lowrance.com> Content-Type: text/plain; charset="us-ascii" I'm using an FPGA to verify an ASIC which is using the I2C core. I'm getting a mismatch between the RTL simulation & the actual FPGA gates when writing to the I2C CR (command register). I setup the 2 prer bytes with known values. Then when I write the cr register, the value written to the cr overwrites the prer(7:0). This is the case only in the FPGA. In rtl simulation, it works as expected. Upon further examination of the rtl code, I think I have found an issue. Please correct me if I'm wrong. Here's the code snippet with the case statement... // generate registers always @(posedge wb_clk_i or negedge rst_i) if (!rst_i) begin prer http://www.opencores.org/forums/cores/attachments/20050225/fa4df2e5/attachment-0001.bin ------------------------------ Message: 2 Date: Sat, 26 Feb 2005 16:05:07 +0800 From: "=?gb2312?B?zPrKrw==?=" winglion at 21cn.com> Subject: [oc] what opensource tools to use To: "cores" cores at opencores.org> Message-ID: 0S949773839282.00439 at send6.inner-21cn.com> Content-Type: text/plain; charset="gb2312" I fount that 80% of gays here vote to use opensource tools For me ,It's a real new idea. please tell me what opensource sofewate you use for disigning a core(sim, syn ) and sch pcb tool! ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡winglion at 21cn.com ¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡¡2005-02-26 ------------------------------ Message: 3 Date: Sat, 26 Feb 2005 14:24:22 -0500 From: Mike Delaney mmdst23 at gmail.com> Subject: Re: [oc] what opensource tools to use To: Discussion list about free open source IP cores cores at opencores.org> Message-ID: ea9d9b97050226112454db2e48 at mail.gmail.com> Content-Type: text/plain; charset=UTF-8 For designing a core, that's a hard question. Did you look at the EDA Tools list on the opencores site, http://www.opencores.org/projects.cgi/web/edatools/eda_tools ? I think there is at least one free (beer) simulator, and there is at least one open source simulator, but I'm not sure how they work. From the web site of one I found (after quickly trying a couple of the links) "TyVIS allows you to simulate and execute VHDL code that has been translated into the TyVIS C++ intermediate form." I took a quick look at the manual, but it seems to suggest that using vendor-spefic parts, such as block RAMs, or ASIC multipliers or DSP blocks/slices, *might* be possible but it's not mentioned in the manual (at least it's not in the table of contents). I've never seen an open source synthesis tool, except for one project that's been dead for a long time. Maybe take a look at this: http://www.opencores.org/forums.cgi/cores/2004/05/000757 Honestly, I'm not even aware of a free (beer and legal) version of the tools from either Xilinx or Altera, although they both have a free windows version that includes a special (ie. SLOW) version of ModelSim. I've heard rumors that the next Xilinx release will have a Linux version of Webpack, but even if true, it won't be out until May. However, Webpack dosen't support all of the Xilinx chips and lacks some of the other features of the full Xilinx tools, which do have a current Linux port, but it costs about $2.5k For a PCB Tool, check out gEDA. Mike On Sat, 26 Feb 2005 16:05:07 +0800, é"çŸ³ winglion at 21cn.com> wrote: ------------------------------ Message: 4 Date: Sat, 26 Feb 2005 14:53:12 -0500 From: "Michael Hordijk" hoffbrinkle at hotmail.com> Subject: [oc] Re: what opensource tools to use To: cores at opencores.org Message-ID: 1 at sea.gmane.org> I've been using GHDL as much as I can for simulation. It's effective, and pretty robust considering it's not that old. There's not much it can't do (it can run a DLX processor and the LEON1 SPARC processor). It's a native VHDL compiler (i.e. it does not translate to intermediate C/C++ or anything). It's written in ADA as a front end to GCC. The developer is easy to get a hold of and responsive to fixing bugs, and it's being actively developed. http://ghdl.free.fr I've had no problems using the above simulator with any of the Xilinx cores I use. Obviously, inferred parts are no problem. It's compiled everything I need from unisim and XilinxCoreLib with no problems. Supports VHDL 2002, etc. I would highly recommend it as an alternative. I haven't gotten to using it on a large design, so I can't say how fast or slow it is compared to, say, ModelSim or what have you. But "free" goes a long, long, long way to making up for that. Think how much computing resources you could buy for the cost of single SE floating license... - hoffer ------------------------------ Message: 5 Date: Sat, 26 Feb 2005 17:31:11 -0500 From: Mike Delaney mmdst23 at gmail.com> Subject: Re: [oc] Re: what opensource tools to use To: Discussion list about free open source IP cores cores at opencores.org> Message-ID: ea9d9b97050226143163ae6b22 at mail.gmail.com> Content-Type: text/plain; charset=US-ASCII Doh! I forgot that Xilinx gave out the source to the behavioral libraries for all the ASIC cells. Sorry about that. Mike On Sat, 26 Feb 2005 14:53:12 -0500, Michael Hordijk hoffbrinkle at hotmail.com> wrote: ------------------------------ Message: 6 Date: Sun, 27 Feb 2005 10:15:32 +0100 From: "Richard Herveille" richard at herveille.net> Subject: RE: [oc] I2C Core RTL Simulation / FPGA mismatch... To: jeff at lowrance.com>, "'Discussion list about free open source IP cores'" cores at opencores.org> Message-ID: 20050227092816.18FDE862F0 at mail.herveille.net> Content-Type: text/plain; charset="us-ascii" Hi Jeff,

Sorta.



You're right. I fixed it and uploaded a new version.
I also fixed the scl/sda delay issue in the testbench.

You either use the full_case statement, or you add a default statement. In this case we need the default statement. Please download the latest version from OpenCores. Cheers, Richard ------------------------------ Message: 7 Date: Tue, 01 Mar 2005 14:06:57 +0200 From: Nikolaos Kavvadias nkavv at physics.auth.gr> Subject: Re: [oc] Re: what opensource tools to use To: Discussion list about free open source IP cores cores at opencores.org> Message-ID: 42245AE1.4050101 at physics.auth.gr> Content-Type: text/plain; charset=ISO-8859-1 -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Mike Delaney wrote:

Please, could you refine on your statement? Any links to the Xilinx
stuff???

-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.0 (MingW32) Comment: Using GnuPG with Thunderbird - http://enigmail.mozdev.org iD8DBQFCJFrhMPiy0tCWlz4RApCaAKCdV9ZCpUG3PiIZyNfPwri5RCpXRQCeOx+V uncMRLR4G3C54AZYU0+TcP0= =XBHb -----END PGP SIGNATURE----- ------------------------------ Message: 8 Date: Tue, 1 Mar 2005 09:59:48 -0500 From: Mike Delaney mmdst23 at gmail.com> Subject: Re: [oc] Re: what opensource tools to use To: Discussion list about free open source IP cores cores at opencores.org> Message-ID: ea9d9b97050301065932beac9c at mail.gmail.com> Content-Type: text/plain; charset=US-ASCII On Tue, 01 Mar 2005 14:06:57 +0200, Nikolaos Kavvadias nkavv at physics.auth.gr> wrote:

Well, the only way I know of (for free) is to download Xilinx Webpack
and install it. Look in the $XILINX/vhdl/src directory. So you'll
still need a Windows box, but the source is also included with the
other (costly) versions of the Xilinx tools. I'm not sure if they do
have a seperate download for it or not.

------------------------------ Message: 9 Date: Tue, 1 Mar 2005 09:53:49 -0800 From: "Sheila Carey" sheilapcarey at demosondemand.com> Subject: RE: [oc] Re: what opensource tools to use To: "'Mike Delaney'" mmdst23 at gmail.com>, "'Discussion list about free open source IP cores'" cores at opencores.org> Message-ID: 20050301175353.4976.3932 at hm-pop1.solinus.com> Content-Type: text/plain; charset="US-ASCII" And you'll find 16 Xilinx training sessions (free) here: http://www.demosondemand.com/dod/proddemos/vendors/pd_xilinx.aspx -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Mike Delaney Sent: Tuesday, March 01, 2005 7:00 AM To: Discussion list about free open source IP cores Subject: Re: [oc] Re: what opensource tools to use On Tue, 01 Mar 2005 14:06:57 +0200, Nikolaos Kavvadias nkavv at physics.auth.gr> wrote:

Well, the only way I know of (for free) is to download Xilinx Webpack and
install it. Look in the $XILINX/vhdl/src directory. So you'll still need a
Windows box, but the source is also included with the other (costly)
versions of the Xilinx tools. I'm not sure if they do have a seperate
download for it or not.

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