Hi everyone,

I'm just starting experimenting with FPGAs as a student, so I decided to try to use I2C as an experiment to access the EEPROM. I'm using this core ported to the Avalon bus: http://opencores.org/project,i2c, which I obtained from here: http://www.alterawiki.com/wiki/I2C_(OpenCores)

If anyone of you has used this before, can you tell me how to configure the core to be in either master or slave mode?

I'm assuming that is required because it doesn't give me any signal at the export pins out of the box (SDA and SCL change only in software, no effect on hardware when monitoring pins using a logic analyser).

I'm using Quartus 12, with SOPC Builder and Nios II Build Tools for Eclipse.

Thanks a lot! :)

2 salmanarif

In original "I2c_opencores_12.0.zip" archive from "alterawiki" you can find "I2c_opencores_12.0.zip\i2c_opencores\Docs/I2C_tests.c" file (and "I2c_opencores_12.0.zip\i2c_opencores\HAL" folder contains a lot of usefull information), which contains almost all you need to know about cfg for this core.
Also you can use I2c_opencores_12.0.zip\i2c_opencores\Docs/i2c_specs.pdf" for deeper understanding of the core.
And regarding "master/slave" configuration - you can read "i2c_specs.pdf" document and find that this IP core have only MASTER functionality.

Thanks a lot. I've managed to get it up and running.