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Cordic with generic port width
by Unknown on Mar 4, 2005 |
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I have added generic port widths to Richards rectangular to polar cordic
core. I would like to make it available to opencores. How do I go about? Can Richard add it to his versions? henning |
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Cordic with generic port width
by Unknown on Mar 4, 2005 |
Not available! | ||
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Yes I can ... Send me the files, I'll verify them and check them into CVS. Cheers, Richard
-----Original Message-----
From: cores-bounces at opencores.org
[mailto:cores-bounces at opencores.org] On Behalf Of h.larsen at risoe.dk
Sent: Friday, March 04, 2005 5:07 PM
To: cores at opencores.org
Subject: [oc] Cordic with generic port width
I have added generic port widths to Richards rectangular to
polar cordic core. I would like to make it available to
opencores. How do I go about?
Can Richard add it to his versions?
henning
_______________________________________________
http://www.opencores.org/mailman/listinfo/cores
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RE: Cordic with generic port width
by Jas on Mar 7, 2011 |
Jas
Posts: 3 Joined: Nov 19, 2010 Last seen: Mar 7, 2011 |
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Hi,
I would like to ask if u come across CORDIC base sine and cosine computation? I would like to implement it in Verilog HDL. So far as I understand, module instantiation is not allowed inside a for loop or always statement. So, if i want to implement a iteration loop, how can I develope the code? Does all the input and output need to be in signed values? How do we represent the inputs in binary format? what is the data format used? do we allocate the fractions bits? I am confused with this part. On top of that, for the angle input, say 30 degree, how do we represent it in a 16bits binary? Thx. I really look forward for your reply. As I really need help. Regards, Jas |
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