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FIFO coregen uninitialized output by Sugam on Oct 23, 2013			Sugam Posts: 1 Joined: Oct 23, 2013 Last seen: Dec 10, 2013
Hi, I am trying to simulate a 1024x16 FIFO using coregen using VHDL. I have declared the entity myself and copied the remaining code from .vho file of the coregen (as explained in various online tutorials). Although my code is being sythesized correctly, in simulation, I am getting a warning like:- WARNING:Simulator:29 - at 0 ns: Warning: No entity is bound for inst and the output is coming 'uninitialized' (red lines) i have attached the code as well Please help!![q]<a href="uploads/1382520990_coregen code.txt">coregen code.txt</a> (1 kb)[/q] Hi, I am trying to simulate a 1024x16 FIFO using coregen using VHDL. I have declared the entity myself and copied the remaining code from .vho file of the coregen (as explained in various online tutorials). Although my code is being sythesized correctly, in simulation, I am getting a warning like:- WARNING:Simulator:29 - at 0 ns: Warning: No entity is bound for inst and the output is coming 'uninitialized' (red lines) i have attached the code as well Please help!! coregen code.txt (1 kb)

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