Hi everyone,

I have worked on an IIR core (order "2") that can run at 100 Msamples/s on a 100 MHz clock using the scattered look-ahead technique. Of course, I used Matlab (Octave would work too) to help analyze the quantization of the filter. I was wondering if anyone would find any interest for this kind of core?

In order to a have a "generic core" there are basically 3 solutions :

1 - Use a lot of generics in the VHDL module, 1 generic for the numerator coefficient size, 1 generic for the accumulator size, 1 generic for the input size, 1 generic for the output size, 1 generic to decide whether one wants saturation or wraparound, etc. This could be cumbersome as it can make the code almost unreadable.

2 - Use an Octave (Matlab) function to create a vhdl RTL file. The function arguments would include, the number of bits for the input, the coefficients, number of bits for the output, saturation, etc.. The function would also generate some kind of testbench to test the generated VHDL RTL file. The RTL file would be easier to understand that way, but the actual source file would be the octave script calling the octave function.

3 - Create a non-generic VHDL file (except for the coefficients I guess...) but document how to modify the VHDL file if one wants to use more bits or less bits for the coefficients, input, etc. For example, on some architectures it might make sense to use 25-bit coefficients.

SO basically, do you think this kind of core would be a good idea on opencores? If so, which solution do you prefer to make this core "generic".