Hi,

Am trying to Generate a PWM signal using VHDL and the Device is Actel with Standard speed.
The frequency input is from the processor, where i have used a binary up counter which counts from 0 to the limit written by processor.

The duty cycle of the pulse required is 90% and 10%.
The ON time of the pulse is also written by the processor, so when counter starts counting (at 0 i will set the pulse high) and when the number of counts reaches the TON value, i will set the pulse to low.

With the above method, am able to generate the pulse as required.

But the problem is, the counter used is 18 bit up counter for my frequency range.
As the counter size is too much, am facing issues with timing and post layout simulations are failing.

Can anyone propose a new method and help me out from this issue ??

I'd use an LFSR instead of a binary counter for 18-bit counting. You never need worry about the delay of an LFSR.

I'd use an LFSR instead of a binary counter.

Hi Fiedel,

Thank you.. i will try with the LFSR and get back with the results