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OCIDEC3 testbench
by Unknown on Mar 22, 2005
Not available!
I've just started looking at the abovementioned core and its associated testbench. Out-of-the-box it fails fairly early on in the piece... I've managed to find that problem... The main test look was calling wb_wr4 with a delay value of 0 for the 1st iteration of the test. In this case stb is being de-asserted and reasserted immediately and the cycle never completes. I simply changed the starting value of the loop to '1' but I'm wondering why it failed in the first place? iotest1 now completes with 0 errors. iotest2 fails immediately but I'm yet to look into it. Regards, -- Mark McDougall, Software Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
OCIDEC3 testbench
by Unknown on Mar 22, 2005
Not available!
Mark McDougall wrote:

iotest2 fails immediately but I'm yet to look into it.
OK, so it would seem that the testbench is for OCIDEC1 only, given the return code on the STAT register. However, since they're supposedly backwards-compatible, I've changed the expected test result and will forge ahead!?! Now I get setup violations... # *** MODE SELECT: PIO mode: 0 iordy enable: 0 # ** Error: P:/MK7/fw/ide/ide at a/bench/ata_device.v(227): $setup( ata_cs0:455 ns, posedge ata_dior &&& ata_rst_m0:515 ns, 70 ns ); # Time: 515 ns Iteration: 4 Instance: /test/a0 # *** MODE SELECT: PIO mode: 0 iordy enable: 1 # ** Error: P:/MK7/fw/ide/ide at a/bench/ata_device.v(227): $setup( ata_cs0:86915 ns, posedge ata_dior &&& ata_rst_m0:86975 ns, 70 ns ); # Time: 86975 ns Iteration: 4 Instance: /test/a0 Investigations continue... -- Mark McDougall, Software Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
OCIDEC3 testbench
by Unknown on Mar 23, 2005
Not available!
Mark McDougall wrote:

Now I get setup violations... # *** MODE SELECT: PIO mode: 0 iordy enable: 0 # ** Error: P:/MK7/fw/ide/ide at a/bench/ata_device.v(227): $setup( ata_cs0:455 ns, posedge ata_dior &&& ata_rst_m0:515 ns, 70 ns ); # Time: 515 ns Iteration: 4 Instance: /test/a0
Interesting that the io_test2 task writes new timings to PCTR which violate these specs immediately before running the tests... is this *supposed* to happen??? Is this testbench meant to run without errors out-of-the-box, or am I doing something stupid? I can't seem to find any doco on the bench itself... Regards, -- Mark McDougall, Software Engineer Virtual Logic Pty Ltd, http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266
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