Most of the cores seem to be written in Verilog, but
there are some SystemC ones. Maybe a "SystemC" entry should be added
to the language selection for project browsing.

Philipp

As you are toalking about systemC... I'm wondering if there is free softwares that help at modeling designs in systemC ??

Francis

Francis, there's a video seminar on SystemC online at: http://www.demosondemand.com/dod/feat_cont/seminars/aldec.aspx -----Original Message----- From: cores-bounces at opencores.org [mailto:cores-bounces at opencores.org] On Behalf Of Ielsch Francis Sent: Thursday, March 31, 2005 8:20 AM To: Discussion list about free open source IP cores Subject: AW: [oc] SystemC As you are toalking about systemC... I'm wondering if there is free softwares that help at modeling designs in systemC ?? Francis _______________________________________________ http://www.opencores.org/mailman/listinfo/cores

For who have interests around SystemC, look at the site of SystemC community www.systemc.org On Thu, 31 Mar 2005 08:43:53 -0800, Sheila Carey sheilapcarey at demosondemand.com> wrote:

Ielsch Francis wrote:

What do you mean about "help at modeling". As far as I know the original idea behind SystemC wasn't synthesis but specification. For the last case: the group that designed SystemC also released the C++ libraries to implement it. I downloaded SystemC 2.1 beta 11 from the oficial site. But that's just plain *SystemC*: a C++ library to generate Hw specifications as binaries. About synthesis: we don't have much free software synthesis tools. In fact I think not even one for FPGAs. Some people told me that SystemC is new and the EDA tools that implements synthesis using a subset of SystemC aren't mature. The tools doesn't agree on what to generate and sometimes generates things that behave in different ways (tool dependant) and sometimes too far from optimal. SET -- Salvador Eduardo Tropea (SET). (Electronics Engineer) Visit my home page: http://welcome.to/SetSoft or http://www.geocities.com/SiliconValley/Vista/6552/ Alternative e-mail: set at computer.org set at ieee.org Address: Curapaligue 2124, Caseros, 3 de Febrero Buenos Aires, (1678), ARGENTINA Phone: +(5411) 4759 0013

Hello, Will one day OpenCores support SystemC ? Here are some very interesting start points : https://unisim.org/site/ http://digilander.libero.it/systemcfl/ http://www-ti.informatik.uni-tuebingen.de/~systemc/download_content.html http://www.ecsi-association.org/ecsi/projects/default.asp http://icodes.offis.de/index.php *Interesting projects : http://openeda.si2.org/ http://www.opensparc.net/ http://opengraphics.org/ http://www.power.org/home http://bbrv.blogspot.com/2006/09/cat-is-out-of-bag.html Best Regards, Will

William DUCK wrote:
Hi Will, There are projects in SystemC on opencores. Have you looked at http://www.opencores.org/browse.cgi/by_category ? [...] Your post got me looking for more information about SystemC, one link I did not see in your post is http://www.systemc.org Cheers, Guenter

Will, There's absolutly nothing keeping you from posting a SystemC project, but what synthesis tools support SystemC? More importantly, what free, or even cheap (in EDA terms, say http://www.esperan.com/livecd/index.html It has some examples, a small desktop, and SystemC set up with GTKWave. It might be the quickest way for someone to get started, at least in simulation. Mike On 10/12/06, William DUCK guillaume.fortaine at wanadoo.fr> wrote:

For sure .. :)

http://www.systemcrafter.com/ http://www.ecsi-association.org/ecsi/projects/odette/synthesis.html http://icodes.offis.de/ Thank you Mike for the link with the liveCD and to point out the weaknesses of SystemC :) Best Regards, Will

Hello,

There are some cores in SystemC at opencores, for example a SystemC USB
core, a SystemC AES core, a SystemC DES core, a SystemC MD5 core.
There are also uploaded at opencores a tool called SystemC to Verilog
synthesizable subset translator that converts a SystemC description to a
equivalent Verilog one that can be synthesizes with any standard RT
synthesis tool.

Best Regards

Javier Castillo

Dear Mike, System Crafter SC (http://www.systemcrafter.com/) combined with xst is a cheap option for Xilinx FPGAs. It costs US$ 2,995.00 (http://www.eetimes.com/showArticle.jhtml?articleID=174401620. Thanks. Jardel Silveira. Development Engineer jardel at lesc.ufc.br http://www.lesc.ufc.br Mike Delaney wrote: -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 256 bytes Desc: OpenPGP digital signature Url : http://www.opencores.org/forums.cgi/cores/attachments/20061013/0b562725/signature.pgp

javier.castillo wrote:
[...]


Hi Javier,

That is a great tool, so that brings the use of SystemC in the reach for
an open source only approach.

Are you aware whether there is a possibility to use SystemC as a
co-verification language in connection with a Verilog simulator for
example. Like is there a PLI interface available that makes it possible
to create a test bench in SystemC and verify Verilog logic with that?

Or is that the purpose of the Verilog to SystemC convert?

Cheers,

Guenter

Hello,

Modelsim supports SystemC-Verilog cosimulation. I think NC-sim also can.

Regards

Javier Castillo

There's also a library called SCV that's a verification addon for SC. Mike On 10/13/06, Günter Dannoritzer dannoritzer at web.de> wrote: