Hi Guys,

ive been doing some research but i havent found a decent solution to my problem thus far. i would like to implement some DRAM controller onto a xilinx fpga so i can address no less then 1GB of memory into a system that uses 32address lines and WR/RD etc control signals and 32/16/8bit addressing. (i.e. for example some vintage 80386 or 80486) instead of using multiple SRAM modules todo this i would like to use 1-4 DIMMS from the DDR or DDR2 or DDR3 specification and a suitable FPGA DRAM controller to refresh and interface the DRAM DIMMs so my CPU core sees the fpga dram controller as "transparent" and only sees the installed address space. could anyoone offer me a sugggestion as to what the simplest way todo this would be or a plan of attack?

im very new to memory controllers so please excuse me.

I discovered recently the same issue: I want to use some DDR2 SDRAM in my SOC, running on a Xilinx Spartan-3.
What I found on OC is

-http://opencores.org/project,wb2mig
(yet another skeleton in the closet, no work was done)

-http://opencores.org/project,sdr_ctrl
(is a DDR controller for a specific part, not suitable for me)

-http://opencores.org/project,ddr2_sdram
(a system, which is based on Xilinx's MIG)

I came up with the solution to realize something like explained in the first project: a bridge between Xilinx MIG core and the Wishbone bus.
This would have the advantage, that different MIG setup's might be used (for different RAM parts, different boards etc.)

I wrote the author of the first link for getting any info / status, but haven't got any response.

If you are interested, I can give you some updates in a few weeks (it my approach works).
Or if you are interested, we can work together on such a bridge project.

What language are you planning to use, VHDL or Verilog?

I was also looking for the same wb->ddram interface few months ago, and i tried to write it myself, but then i noticed that if you try to simulate the ddram, the simulation runs extremely slow. It takes hours to simulate few clock cycles so i left this task for later... Are you planning to use the Hardware Co-Simulation?

Regards
Klemen

So, I have done a logic analyzer project that uses a DRAM controller on a Spartan-3E.

It is written in Verilog, and is pretty bare-bones. It is a slight modification from the DRAM controller supplied by OpalKelly for their stuff.

GPL and all that. Links and project info can be found here:
http://www.burke.tv/Tom/Cookbook/LogicAnalyzer/index.shtml

A generic Wishbone MIG wrapper would be nice to have. I recommend you to take a look at the one we use for the Atlys board for inspiration. https://github.com/openrisc/orpsoc-cores/tree/master/systems/atlys/rtl/verilog/xilinx_ddr2

@fogl Yes, running event-based simulations with vendor memory models is painfully slow. One way to get around this would be to make a simple HDL model of the MIG interface instead and use that instead of the complete memory controller

My plan was to implement it in Verilog. I did a few trials with a simple implementation.
The RTL simulation result looked good and I was able to run the simulation with Icarus.

I also tried to bring the design on my Spartan FPGA, but it doesn't work.
The interaction with the MIG core looks good, but when reading from the RAM, I never get any high bit (everything is always 0).
After hours of searching, I tried the example provided by Xilinx and it is not working. too.
Now, I'm running out of ideas and it seems, that my RAM component is just broken.