I have a board with spartan xc3s50AN FPGA and 7 (8ch 16bit)ADCs with QUAD spi => therefore 28 SPI signals in to FPGA
The prototype worked but at that time I wasn't using all the inputs.

The code simultaneously writes 28bits of data to 32bit long arrays, after the SPI transver is completed then each array is split in to 2 16bit arrays which represent a single measurement and send to FIFO.

When I try to implement the full design I receive a message "cannot fit design" if I cut 4 pairs of signals it works.

Basically what I need is size efficient version on how to simultaneously write 28bit COLUMS in to same kind of data matrix and the read ROWS from that matrix.